ASIC Design Verification Engineer

Minimum qualifications:

• 
  Bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience.
  
  
• 3 years of experience in the formal verification domain.
• Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem or Full chip level.
• Experience with scripting languages (e.g., Python/Perl, and TCL).
• Experience in formal verification applications (e.g., sequential equivalence checking, and connectivity checking) and data-path verification.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Science, or a related field.
• Experience working with one or more formal verification tools, such as JasperGold, VC Formal or Questa Formal.
• Experience with formal sign-offs of industry ASIC designs.
• Knowledge of formal methodology and formal abstraction techniques.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Plan the formal verification strategy and create the properties/constraints for digital design blocks.
• Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
• Contribute improvements to methodologies to enhance formal verification results.
• Architect and implement reusable formal verification components.