ASIC Digital Design Engineer

Salary:Market related Reference:114808 Senior / Staff Digital Design Engineer – High-Performance ASICs We are seekingSenior and Staff Digital Design Engineersto take end-to-end ownership ofhigh-speed, real-time data-processing silicon—from early algorithm modelling through verified RTL and silicon bring-up. You will join a multidisciplinary team developing next-generation OTPUs at the intersection ofdigital, optical, and mixed-signal domains. This role is ideal for engineers with a deep background in CMOS digital design, a solid grasp of semiconductor fundamentals, and a passion for buildingreliable, high-performance digital circuitsthat enable breakthrough AI hardware.Responsibilities • Architect and implement high-throughput digital pipelines(multi-GSPS inputs, deep pipelining, handshake protocols) in advanced CMOS nodes.Prototype rapidly in FPGA(AMD/Xilinx, Intel or equivalent): build real-time demos, validate transceivers, and feed learnings back into ASIC design. • Model and validate algorithmsin MATLAB/Simulink or Python, ensuring functional equivalence through to gate-level sign-off. • Own RTL development(SystemVerilog / Verilog / VHDL) including synthesis, static timing closure, and advanced verification (formal and constrained-random). • Optimise PPA (power, performance, area)to achieve aggressive bandwidth-per-watt targets. • Collaborate cross-functionallywith optical, mixed-signal, and software teams on converter interfaces, CDC, and firmware integration. • Mentor junior engineers, lead reviews, and drive adoption of best-practice design methodologies.Skills & Experience • 7+ years of digital design for high-performance ASICs or SoCs, with ownership of at least one real-time streaming product. • Proven success closing timing in multi-hundred-MHz to multi-GHz clock domains, and integrating high-speed IP (SerDes, HBM/DDR, PCIe, 100 GbE or similar). • Strong experience with industry EDA flows: synthesis, STA, CDC/RDC, lint, power intent (UPF/CPF), and gate-level simulation. • Hands-on FPGA prototyping: constraint management, transceiver tuning, hardware bring-up and debug. • Proficiency in algorithm modelling (MATLAB/Simulink or Python/NumPy), including fixed-point analysis and test-vector generation. • Solid grounding in digital signal processing, computer architecture, and semiconductor physics. • Excellent communication and teamwork skills; comfortable operating in afast-moving, exploratory environment.Nice to Have • Tape-out experience at 22 nm. • Knowledge ofcoherent optical linksor photonic-electronic co-design. • Familiarity with AI/ML compute architectures (systolic arrays, tensor processors). • Contributions toopen-source RTL, verification frameworks, or FPGA platforms.INDTEDA