CPU Verification Engineer

Introduction
As a Hardware Developer at IBM, you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today's market.

Your Role and Responsibilities
As a Functional Verification Engineer, you will play a crucial role in ensuring the quality and reliability of IBM server processors, SOCs, and ASICs. Guiding the development of verification environments and testbenches, you will be instrumental in crafting test strategies and driving verification coverage closure. Your expertise in functional verification methodologies and programming skills will be essential in delivering high-quality designs for IBM servers.

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• Verification Environment Development: Guide the development of verification environments, testbenches, and test cases for IBM server processors, SOCs, and ASICs.
• Collaborative Debugging: Collaborate with design teams and key stakeholders to debug and resolve logic design issues, ensuring the delivery of high-quality designs.
• Coverage Closure: Drive verification coverage closure by developing comprehensive test plans and strategies, ensuring thorough verification of IP/unit/block-level designs.
• Programming: Utilize object-oriented programming skills in C/C++ and scripting languages like Python/Perl to write complex test scenarios and automate verification processes.
• Ongoing Skill Development: Develop proficiency in IBM functional verification tools and methodologies, staying updated with the latest advancements in the field.

• Experience in the following areas
• Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification.
• Core architecture/micro-architecture verification
• Multi-processor Cache Coherency/Network on Chip/Memory Hierarchy verification.
• AXI/AHB/ACE/ACE-lite/CHI/On Chip System Fabric interface verification or any other Processor/SoC coherency transport interconnect fabric verification.
• Minimum one full life cycle leadership experience of a processor/SoC verification flow with focus on Coherency Transport Interconnect and/or Network on Chip Verification
• Good object-oriented programming skills in C++/SystermVerilog, scripting languages like Python/Perl.
• Verification knowledge in Clock domain crossing and reset domain crossing
• Knowledge of functional verification methodology like UVM/OVM
• Knowledge of HDLs (VHDL/Verilog)
• Developed test plans and test strategies for IP/unit/block level verification of Coherency Transport Interconnects
• Worked on multiple levels of verification (unit/element/sub-system/system level)
• Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow
• Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails
• Experience in driving verification coverage closure.

• Stress testing and ability to identify corner case scenarios.
• Good understanding of computer system architecture and microarchitecture.
• Knowledge in IP Integration and SoC level verification.
• Knowledge of design patterns in programming