FE/RTL Designer

About Bitdeer:

Bitdeer Technologies Group (Nasdaq: BTDR) is a leader in the blockchain and high-performance computing industry. It is one of the world’s largest holders of proprietary hash rate and suppliers of hash rate. Bitdeer is committed to providing comprehensive computing solutions for its customers.

The company was founded by Jihan Wu, an early advocate and pioneer in cryptocurrency who cofounded multiple leading companies serving the blockchain economy. Mr. Wu leads the company as Founder, Chairman, and CEO, while Matt Linghui Kong serves as Bitdeer’s CBO and provides leadership through deep industry knowledge and technology expertise.

Headquartered in Singapore, Bitdeer has deployed mining data centers in the United States, Norway, and Bhutan. It offers specialized mining infrastructure, high-quality hash rate sharing products, and reliable hosting services to global users. The company also offers advanced cloud capabilities for customers with high demands for artificial intelligence.

Dedication, authenticity, and trustworthiness are foundational to our mission of becoming the world’s most reliable provider of full-spectrum blockchain and high-performance computing solutions. We welcome global talent to join us in shaping the future.

What you will be responsible for: 

• Implement Verilog RTL for various sections of the NPU/CPU/NoC core pipeline and related logic.
• Work with hardware and software engineers to define high-level architecture and microarchitecture of next-generation high-performance AI cores.
• Support synthesis, timing closure, power reduction, and floorplanning efforts to optimize performance and efficiency.
• Contribute to design verification and assist in debugging issues across pre-silicon and post-silicon stages.

How you will stand out:

• Master’s degree (preferred) or Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture
• Verilog RTL development experience with industry-standard tools in a CPU, SoC, or ASIC environment.
• Strong understanding of NPU/CPU architecture and logic design.
• Familiarity with power-saving techniques and microarchitecture development.
• Awareness of synthesis, place & route (P&R), and timing closure concepts.
• Strong problem-solving and debugging skills.
• Background in ASIC implementation, particularly synthesis flow and static timing analysis.
• Knowledge of Design-for-Test (DFT) and Design-for-Debug (DFD) techniques.
• Experience with clocking, reset sequences, power-up sequences, and power management.
• Exposure to physical design and verification methods.
• Familiarity with x86 or ARM ISA.
• Comfort with scripting languages (Perl, Shell, TCL) to automate design tasks.

What you will experience working with us:

• A culture that values authenticity and diversity of thoughts and backgrounds;
• An inclusive and respectable environment with open workspaces and exciting start-up spirit;
• Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
• Ability to contribute directly and make an impact on the future of the digital asset industry;
• Involvement in new projects, developing processes/systems;
• Personal accountability, autonomy, fast growth, and learning opportunities;
• Attractive welfare benefits and developmental opportunities such as training and mentoring.

--------------------------------------------------------------------

Bitdeer is committed to providing equal employment opportunities in accordance with country, state, and local laws. Bitdeer does not discriminate against employees or applicants based on conditions such as race, colour, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.