FPGA Design & Verification Engineer Lead
Company
York Space Systems
Location
Greater Denver Area
Type
Full Time
Job Description
York Space Systems was founded to radically improve spacecraft affordability and reliability, transforming, and enabling next-generation space mission operations worldwide. Today, York is one of the most innovative aerospace companies, specializing in end-to-end customer solutions and the rapid production of spacecraft platforms. York’s complete Space Segment Solution includes spacecraft production, payload integration, system integration & test, launch services, ground segment services, and mission operations, enabling customers to leverage York’s existing technology solutions to get to orbit rapidly and responsively. We’re looking to expand our team across the board.
York Space Systems LLC is seeking a talented FPGA Design & Verification Engineer to join the Electrical Systems team. The successful candidate will be a creative problem solver and life-long learner who continually seeks a deeper understanding and expertise of digital logic design. They must be attentive to detail and disciplined at documentation to ensure quality and maintainability in our products.
RESPONSIBILITIES
- Design, develop, and verify complex FPGA designs.
- Register Transfer Level (RTL) coding in (System) Verilog and/or VHDL.
- Debug and validate designs in a lab environment.
- Generate design documentation.
- B.S. or M.S. in Electrical and/or Computer Engineering.
- ​Ability to thrive in a collaborative “small-team” culture and environment.
- Excellent communication and interpersonal skills, including a demonstrated ability to interact with customers, management, and peers.
- Knowledge and deep understanding of RTL coding using Hardware Description Languages (HDL).
- Experience with SystemVerilog Object-Oriented Programming.
- Design experience including design, debug, documentation, and review of RTL design blocks, including an understanding of reset and clocking architecture design.
- Ability to debug and validate designs with use of lab tools such as oscilloscopes and logic analyzers.
- Python, TCL, Make, and shell scripting.
- Experience using ModelSim and/or QuestaSim.
- Experience with UVM, Assertions, and Constrained Random Verification techniques.
- Prior experience working with AMBA Protocols such as AXI or APB.
- Develop and maintain an automated regression test environment.
- Ability to analyze signal timing characteristics and formulate design constraints.
- Knowledge of design techniques for radiation upset mitigation.
- Experience developing signal processing algorithms such as filters, (de)modulators, linear recursive sequence generators, correlators, phase-locked loops, error detection and correction encoders/decoders, timing & synchronization, framing/de-framing, packetization, etc.
Date Posted
09/21/2023
Views
8
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