As a Hardware Engineer at IBM Systems Lab you’ll get to work on the systems
that are driving the quantum revolution and the AI era. Join an elite team of
engineering professionals who enable customers to make better decisions
quicker on the most trusted hardware platform in today’s market.
Lead the architecture design and development of Processor Core Front
end of pipeline units for high-performance IBM Systems.
- Architect and design I-Cache Instruction Fetch Branch Prediction and
Decode units of a high performance processor CPU
- Develop the features present the proposed architecture in the High level
design discussions
- Estimate the overall effort to develop the feature.
- Estimate silicon area and wire usage for the feature.
- Develop micro-architecture Design RTL Collaborate with other Core
units Verification DFT Physical design Timing FW SW teams to develop
the feature
- Signoff the Pre-silicon Design that meets all the functional area and
timing goals
- Participate in post silicon lab bring-up and validation of the hardware
- Lead a team of engineers guide and mentor team members represent
as Logic Design Lead in global forums.
Introduction*
As a Hardware Engineer at IBM Systems Lab you’ll get to work on the systems
that are driving the quantum revolution and the AI era. Join an elite team of
engineering professionals who enable customers to make better decisions
quicker on the most trusted hardware platform in today’s market.
Required Professional and Technical Expertise*
.12 or more years of demonstrated experience in architecting and designing
specific CPU unit(eg. I-Cache Instruction Fetch Branch
Prediction Instruction Decode)
- Hands on experience of different Branch Prediction techniques
- Deep expertise in Out of Order Super Scalar Multi-Threaded Core
Architecture and ISA
- Experience with high frequency instruction pipeline designs
- At least 1 generation of Processor Core silicon bring up experience
- In depth understanding of industry microprocessor designs (e.g. x86
ARM or RISC-V processor designs)
- Proficiency of RTL design with Verilog or VHDL
- Knowledge of at least one object oriented or functional programming
Lead the architecture and microarchitecture design and development of a server class high-
performance Processor CPU for IBM Systems.
- Architect and design Instruction caches Branch Predictors Issue queues
Register Renaming Load Store Execution and other areas of the IBM
processor CPU
- Research novel instruction/data prefetching and branch prediction
architectures.
- Develop the features present the proposed architecture in the High level
design discussions
- Estimate the overall effort to develop the feature.
- Estimate silicon area and wire usage for the feature.
- Develop micro-architecture Design RTL Collaborate with other Core
units Verification DFT Physical design Timing FW SW teams to develop
the feature
- Signoff the Pre-silicon Design that meets all the functional area and
timing goals
- Participate in post silicon lab bring-up and validation of the hardware
- Lead a team of engineers guide and mentor team members represent
as Logic Design Lead in global forums.
Expertise in Out of Order Super Scalar Multi-Threaded Core Architecture
and ISA
- Experience with high frequency instruction pipeline designs
- In depth understanding of industry microprocessor designs (e.g. x86
ARM or RISC-V processor designs)
- Proficiency of RTL design with Verilog or VHDL
- Nice to haves
- Knowledge of verification principles and coverage
- High-level knowledge of Linux operating system
- Knowledge of object oriented languages and scripting languages
- Understanding of Agile development processes
- Experience with DevOps design methodologies and tools
- Experience with high frequency instruction pipeline designs
- In depth understanding of industry microprocessor designs (e.g. x86
ARM or RISC-V processor designs)
- Proficiency of RTL design with Verilog or VHDL
- Nice to haves
- Knowledge of verification principles and coverage
- High-level knowledge of Linux operating system
- Knowledge of object oriented languages and scripting languages
- Understanding of Agile development processes
- Experience with DevOps design methodologies and tools
12 or more years of demonstrated experience in architecting and designing
specific CPU unit(eg. I-Cache Instruction Fetch Branch
Prediction Instruction Decode)
- Hands on experience of different Branch Prediction techniques
- Deep expertise in Out of Order Super Scalar Multi-Threaded Core
Architecture and ISA
- Experience with high frequency instruction pipeline designs
- At least 1 generation of Processor Core silicon bring up experience
- In depth understanding of industry microprocessor designs (e.g. x86
ARM or RISC-V processor designs)
- Proficiency of RTL design with Verilog or VHDL
- Knowledge of at least one object oriented or functional programming
language and scripting language.