NEST Lead - Functional Verification

IBM β€’ BANGALORE, IN

Company

IBM

Location

BANGALORE, IN

Type

Full Time

Job Description

Introduction

As a CPU Processor Verification Engineer you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today’s market.

Your role and responsibilities


  • As a Functional verification engineer you will be working on IBM server processors/SOC or

ASICs used in IBM servers.

  • Lead the development of the verification plans environment testbenches and writing

testcases for the system level in IBM Server Processors.

  • Develop skills in IBM Functional verification tools and methodologies.
  • Work with design as well as other key stakeholders in debugging and fixing logic design

issues and deliver a quality design

  • Work with development team to ensure coverage criteria is met
Required education
Master's Degree
Preferred education
Bachelor's Degree
Required technical and professional expertise


  • 10+ years of experience in Functional Verification Lead of processors or ASICs.
  • 5+ years of experience in the following areas
    • Computer architecture knowledge Processor core design specifications instruction

set architecture and logic verification.

  • Core architecture/micro-architecture verification
  • System level and unit level verification.
  • Multi-processor Cache Coherency/Network on Chip/Memory Hierarchy verification.
  • AXI/AHB/ACE/ACE-lite/CHI/On Chip System Fabric interface verification or any

other Processor/SoC coherency transport interconnect fabric verification.

β€’ Minimum one full life cycle leadership experience of a processor/SoC verification flow with

focus on Coherency Transport Interconnect and/or Network on Chip Verification

β€’ Strong object-oriented programming skills in C++/SystermVerilog scripting languages like

Python/Perl.

β€’ Verification knowledge in Clock domain crossing and reset domain crossing

β€’ Knowledge of functional verification methodology like UVM/OVM

β€’ Knowledge of HDLs (VHDL/Verilog)

β€’ Developed test plans and test strategies for IP/unit/block level verification of Coherency Transport

Interconnects

β€’ Worked on multiple levels of verification (unit/element/sub-system/system level)

β€’ Development experience on Linux/Unix environments GIT repositories and good

understanding of Continuous Integration and DevOps workflow

β€’ Exposure in developing testbench environment write complex test scenario debugging and

triaging fails

β€’ Experience in driving verification coverage closure.

Preferred technical and professional experience

Additional skill preferences

β€’ Stress testing and ability to identify corner case scenarios and System level and unit level verification.

β€’ Good understanding of computer system architecture and microarchitecture.

β€’ Knowledge in IP Integration and SoC level verification.

β€’ Knowledge of design patterns in programming

Apply Now

Date Posted

12/18/2025

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