Principal Engineer, Memory and Interface IP Integration

Working at SambaNova

This role presents a unique opportunity to shape the future of AI and the value it can unlock across every aspect of an organization's business and operations. SambaNova is hiring a senior-level Memory and IP Integration Engineer who will be responsible for the integration and post-silicon bring-up of IO and memory subsystems. In this position, you will play a unique and critical role in the design and productization of the SambaNova DataScale® system and you will be provided with cross-functional learning across the hardware and software stack with opportunities for growth in a fast-growing AI system company.

Responsibilities 

• Engage in architecture definition and evaluate implementation trade-offs with system/chip architects
• Drive the selection of Interface and Memory IPs to meet PPA requirements
• Be responsible for microarchitecture spec, RTL design and integration of 3rd-party IP
• Support the physical design team, review clocking and timing constraints
• Work closely with verification/emulation on feature scoping and test plans
• Drive cross-functional triage effort on complex functional and performance issues
• Take a leadership role in post-silicon bring up of IO and memory subsystems
• Define boot-up initialization and reset flows
• Perform system-level debug and root-cause analysis through bring-up, validation and production phas

Basic Qualifications

• BS or MS in EE, ECE or CS
• 7+ years of experience in silicon development with 3+ years in SOC / IO / memory subsystems

Additional Required Qualifications

• Experience in microarchitecture, logic design, SystemVerilog and UVM design methodology
• Experience in one or more  protocols such as Ethernet, PCIe, CXL, HBM, UCIe
• Experience with on-chip interconnects like AXI or equivalent
• Experience with IP integration related methodology and flows
• Experience working with 3rd-party vendors
• Must have done at least one full-cycle SOC design from concept, all the way to post-silicon bring-up and productization
• Good leadership skills and ability to multi-task and thrive in a dynamic environment

Preferred Qualifications

• NoC (Network on Chip) experience is a plus
• Domain expertise in the Ethernet stack (400G / 800G MAC, PCS, FEC)
• Working knowledge of interfacing to high-speed PHY / PMD
• Experience with sub-system performance modeling and analysis

Annual Salary Range and Level

The base salary for this position ranges from $165,000/year up to $210,000/year. This range is based on role, level, and location and reflects the salary target for new hires in the US. Individual pay within the range will depend on a number of factors, including a candidate’s job-related qualifications, skills, competencies and experience, and location.

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