Senior Design Verification Engineer

Description

Senior Design Verification Engineer (Arteris, Inc. dba Arteris IP; Austin TX): Research, design, develop, and test electronic components and systems for commercial and industrial use. Determine project material or equipment needs and analyze electronics system requirements, capacity, cost, and user needs to determine project feasibility. Develop and debug test benches using UVM (Universal Verification Methodology) to verify RTL design. Define, document, develop and execute RTL verification test and coverage at system level. Conduct performance verification and power-aware verification. Triage Regressions, Debug RTL designs in Verilog and SystemVerilog, write code and functional coverage. Improve and refine verification process, methodology, and metrics. Drive SoC projects from test bench development to verification closure. Oversee verification flow enhancements using Shell scripts, Python and JavaScript.

Salary: $152,000 - $175,000 per year

Send resumes to: HR Recruiting, Arteris, Inc. dba Arteris IP, 900 E. Hamilton Ave., Suite 300, Campbell, CA 95008