AI Hardware Design Verification Engineer

We are seeking an experienced Senior-Level Design Verification Engineer to join our dynamic and innovative team. As a Senior-Level Design Verification Engineer, you will play a critical role in ensuring the quality and reliability of our digital designs through comprehensive verification methodologies. The successful candidate will have a strong background in verification techniques, excellent problem-solving skills, and a passion for delivering high-quality designs.

This job is hybrid, based out of Austin, TX; Santa Clara, CA; Boston, MA; or Toronto, ON.

Responsibilities:

• Develop and execute comprehensive verification strategies to validate complex digital designs, ensuring compliance with specifications and standards.
• Collaborate closely with design teams to understand design requirements and contribute to the creation of verification plans and testbenches.
• Write and execute test cases to verify functionality, performance, and power aspects of the design.
• Perform functional and formal verification to identify and debug design issues and ensure correct design behavior.
• Develop and maintain verification infrastructure, methodologies, and best practices to improve efficiency and productivity.
• Drive the adoption of advanced verification methodologies, tools, and techniques to enhance the overall verification process.
• Mentor and provide technical guidance to junior verification engineers, sharing expertise and best practices.
• Collaborate with cross-functional teams to analyze and resolve system-level issues and ensure seamless integration of the design.
• Stay updated with the latest industry trends, emerging technologies, and verification methodologies to drive innovation and continuous improvement.

Experience & Qualifications:

• Bachelor's or Master's degree in Electrical/Computer Engineering or a related field.
• Proven experience as a Design Verification Engineer, with a focus on complex digital designs.
• Strong knowledge of digital design concepts, including RTL, synthesis, and timing constraints.
• Proficiency in verification methodologies such as UVM (Universal Verification Methodology) and SystemVerilog.
• Experience in developing and executing verification plans, testbenches, and test cases for digital designs.
• Solid understanding of functional coverage, assertion-based verification, and code coverage analysis.
• Proficiency in scripting and programming languages like Python, Perl, or C/C++.
• Familiarity with industry-standard EDA tools and simulation environments.
• Excellent problem-solving and debugging skills, with a keen eye for detail.
• Strong communication and interpersonal skills, with the ability to collaborate effectively in a team-oriented environment.
• Proven ability to work under tight deadlines and deliver high-quality results.