AMS Design Verification Engineer
Job Description
Looking for your next career move, project or freelance opportunity?
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Explore your career possibilities with Talent 101. At Talent 101 we take ownership of our semiconductor customer’s projects, direct hire and contract needs and provide them with the brightest talent that are on top of their game and can make a direct impact on our customer’s business.
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Our customer has asked Talent 101 to identify an AMS Verification Engineer for a 6+ month project located in Dallas, Texas.
In this role you will be supporting a team of top-notch Design Engineers providing verification of Mixed Signal Integrated Circuits. You will be developing test benches, conducting regression testing and working with design engineers to resolve any bugs identified. Additionally, you will be responsible for bug tracking and documentation.
What is required to be successful in this opportunity?
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- 8+ years directly related experience.
- Run simulations and characterize performance of variance analog blocks and sub-systems
- Execute the pre-silicon verification of mixed-signal products
- Create verification plans using datasheets, inputs from engineers / customers, and working closely with systems engineers
- Implement mixed-signal test-benches in Cadence Virtuoso and/or Verilog-AMS to apply stimulus and checks
- Implement automatic checks and measurements to verify behavior and populate a Specification Matrix
- Provide periodic updates on DV status to project participants, management, and customers.
- Work with design and systems teams to close bugs as they arise.
- Work with the EDA team to upgrade tools and flows.
- Review the digital and analog design to provide guidance on Mixed Signal Design for Verification architecture and features.
- Verilog and one of Verilog-A or Verilog-AMS or System Verilog or Specman
- Advanced verification methodologies such as UVM
- Bug tracking, functional coverage, RTL code coverage
- Cadence Virtuoso schematic editor
- Strong knowledge in tool and language usage- AMS, Verilog-AMS, System Verilog, PERL or Python
- Capable of Independent interpretation of specification and system
- Strong understanding of circuits and simulation techniques
- Scripting/coding capability with an automation mindset
Applicants must be at least 18 years or older, must be willing to take a drug test and background check as part of the selection process and must have legal authorization to work in the United States.
For more information regarding Talent101 please visit our website www.talent-101.com. We provide an open-door policy; please feel free to follow up by email [email protected] or by phone 972 503 2101 and ask for a Resource Project Manager to assist you.
Talent101 does not discriminate in practices or employment opportunities on the basis of an individual's race, color, national or ethnic origin, religion, age, sex, gender, sexual orientation, marital status, veteran status, disability, or any other proscribed category set forth in federal or state regulations.
Date Posted
03/27/2023
Views
12
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