ASIC Physical Digital Layout Technical Lead

Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual’s passions, growth, wellbeing and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

Why Ciena:

• You will be a member of a successful team working on the forefront of technological innovation focused on leading edge technologies, flows and products. You will be working with, and learning from, industry recognized experts.
• Our team supports an inclusive, diverse and barrier-free work environment making for empowered and committed employees.
• We recognize the importance of well-being and offer programs and benefits to support and sustain the mental and physical health of our employees and their families.
• Great work deserves recognition. We have a robust recognition program, with ongoing and enhanced awards for exemplary performance.

How You Will Contribute:
The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to Ciena's success in the telecommunications industry. As an ASIC Physical Digital Technical Lead working on large mixed-signal SoC ASICs targeting advanced technology nodes, you’ll play a key role in floorplan development for physical aware synthesis, floorplanning for PnR, implementation of block for place and route, sdc creation and manipulation, CTS, STA study, congestion analysis, power and timing correlation, power integrity, physical verification, and finishing. Your ability to innovate and drive solutions optimized for performance, power and area for the Wavelogic ASICs will be key.

As a Technical Lead of the Digital Layout team, you will:

• Scope the design physical architecture, and work with EDA vendor tools to build, adapt, and maintain a successful flow from netlist to full closure and GDSII generation.
• Partnering with RTL circuit designers and other layout engineers, you will create adequate floorplan, design power grid and clock distribution networks to accomplish optimal performance.
• Understand and navigate the various EDA tool variable, parameters, and attributes to be able to drive the tool for signoff quality and closure with optimal PPA.
• Identify and suggest alternative implementations, recommendations, and solutions pointing out lower power and higher performance trade-offs.
• Work with analog designers and ASIC/SoC in integrating analog blocks. 
• Be responsible for running initial trials of quick PnR to refine the design and correlation. In working with the RTL designers and architects to understand the circuit data flow, you will influence circuit architecture to achieve reliable and closable physical design.
• Implement and apply ECOs to help closure or to apply an RTL feature fix and run and analyze formal verification (LEC or Formality).
• Build and automate a flow via scripting to enhance productivity and effectiveness and enable other backend engineers. In the process, you will interact with tool vendors and technology vendor to drive tool fixes, flow improvements, and perform tool evaluations of new vendor tools and functions.
• Produce a concise status report at various stage of the development and highlight trade-offs.

The above lists are intended to describe the general nature and level of work, and they are not intended to be a comprehensive list of all responsibilities, duties and skills required to be qualified and to be performed by the selected candidate. You will have an opportunity to better understand the role through the interview experience.

What Does Ciena Expect of You:

• Sense of urgency and accountability – what’s important to the customer is important to you; you make getting things done a priority.
• Detail-oriented – you will deliver on objectives through meticulous, thorough, and comprehensive work.
• Problem solver – you possess the ability to analyze and methodically solve complex technical problems using engineering principles and approaches.
• Commitment to learning – you keep abreast of technology developments and are keen to share your knowledge with others.

The Must Haves:

• Minimum Bachelor’s degree in Electrical or other applicable scientific degree coupled with significant experience in ASIC physical digital design and timing closure
• Understanding of the submicron technology nodes full backend ASIC flow and timing/power/area analysis and trade-offs.
• Proven experience working with Genus, Innovus, and Primetime.
• Experience developing scripts to automate tasks throughout the backend flow.
• Experience in working with multiple power domains and knowledge of UPF and SOCV/POCV concepts

Assets:

• Experience with:Tempus, Redhawk/Voltus, and Calibre.

Compensation and Benefits

The annual pay range for this position is $123,200 - $196,800 CAD.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
 

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At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.