ASIC Verification Engineer 3

• You will be a member of a successful team working at forefront of technological innovation focused on innovative technologies, flows and products. You will be working with, and learning from industry-recognized experts. 

• Our team supports an inclusive, diverse and barrier-free work environment making for empowered and committed employees.

• We recognize the importance of well-being and offer programs and benefits to support and sustain the mental and physical health of our employees and their families. 

• Great work deserves recognition. We have a robust recognition program, with ongoing and enhanced awards for exemplary performance. 

How You Will Contribute:

The Wavelogic family of products is widely used in Ciena's optical fiber transmission solutions and is one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for a hardworking digital verification engineer who will be involved in the verification of these products, working within a team of digital design engineers, verification engineers and architects. Your role as a digital verification engineer will be required to propose and implement innovative verification strategies, in order to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products.

• The digital verification engineer is encouraged to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects.

• You are held responsible for the complete and detailed validation of one or more architectural functional blocks by using an appropriate combination of simulation, formal and coverage methods.

• You are encouraged to build the verification, functional coverage and formal verification test plans.

• You are accountable for the creation of the test bench environment and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable.

• You will perform coverage-driven verification, monitor regressions and debug resulting failures with the help of the function's designer.

• Reporting on status updates on a regular basis

What Does Ciena Expect of You: 

• Sense of urgency and accountability – what’s important to the customer is important to you; you make getting things done a priority. 

• Diligence – you will deliver on objectives through meticulous, thorough, and comprehensive work. 

• Problem solver – you possess the ability to analyze and methodically solve complex technical problems using engineering principles and approaches. 

• Commitment to learning – you keep abreast of technology developments and are keen to share your knowledge with others. 

The Must Haves:

• BEng/BSc, MEng/MSc or PhD. level degree in Electrical or computer engineering, computer science .

• Proficiency above the intermediate level with the use of System Verilog, UVM, SVA, and simulators from major vendors.

• A highly motivated self-starter, able to work independently, while being a great teammate

• Ability to methodically address sophisticated technical problems.

• Excellent organization, written and oral (English) interpersonal skills.

• Validated ability to resolve appropriate and comprehensive digital verification and coverage strategies.

Assets:

• Experience with formal verification methods

• Experience with standards and protocols such as OTN/FlexO/B100G, Ethernet (100GE+)

• Experience with using GIT for source code management and revision tracking

• Experience with using Jira for schedule planning, assignment tracking and bug reporting

• Familiarity with programming languages such as Python, Make, bash, object-oriented programming, C, C++, System C