ASIC/SoC System Level Test Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
• 5 years of experience with hardware testing of systems based on custom ASICs or SoC products.
• Experience with Linux/Unix, Python programming, or TCP/IP network configuration.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 10 years of experience with hardware or semiconductor testing.
• Experience implementing secure ASIC/SoC manufacturing solutions (e.g., provisioning, e-fuse programming, or lifecycle management).
• Experience in C#, .NET Framework, C/C , or Perl.
• Knowledge of ASIC/SoC boot process or CPU performance testing.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Our computational challenges are so big, complex, and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Our team designs and builds the hardware, software and networking technologies that power all of Google's services.

As a System Level Test Engineer, you design and build the systems that are the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing and mission-mode operation. Your work has the potential to shape the machinery that goes into our data centers affecting millions of Google users.

In this role, you will help to integrate SoC (System on Chip) technologies into High Performance Computing (HPC) Products. You will develop and automate the system-level manufacturing test of ASIC and SoC to validate performance and screen out bad devices. You will participate in all aspects of System level Test and Product Engineering activities. You will work with ASIC Architecture, Design, and Pre-silicon SoC Verification teams to define test methodologies and implement manufacturing solutions.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $150,000-$223,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Develop System Level Test (SLT) solutions for custom ASIC's and SoC's by specifying hardware and integration requirements, developing software frameworks and test modules, and integrating test cases from silicon validation and system software and test teams
• Partner with data center server and accelerator design teams to realize practical test solutions leveraging system design and test elements
• Partner with hardware and software teams to evaluate functional device yield and performance across various operating conditions, characterize hardware/software interaction, and develop effective production screens to reduce Defective Parts per Million (DPPM).
• Integrate test software and hardware solutions with robotic chip handlers, drive bring-up of the fully integrated solution in internal and partner NPI labs, transfer all collaterals needed for High Volume Manufacturing (HVM) at Offshore Assembly and Test (OSAT) facilities, and provide ongoing HVM support