Chiplet Technologist and Design Integration Technical Lead, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, related field, or equivalent practical experience
• 8 years of experience in front end design
• Experience with SERDES IP integration such as PCIe, USB, D2D UCIe into SoC from feature definition to full design implementation
• Experience with standard bus protocols for interconnect design and with Tapeout of SoC or test chips in process technologies

Preferred qualifications:

• Experience with pre-silicon to post-silicon overall end to end execution
• Experience with post-silicon debug with the latest process technology nodes
• Experience with multiple foundries PDK design
• Strong statistical, data analysis, teamwork, and communication skills

About the job

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

You will be part of Google's Silicon team, developing high performance and low power hardware to enable Google's continuous innovations in mobile devices.

In this role, you will be responsible for selecting and integrating Chiplet technologies, along with other IO interface and design IPs, and develop plans and strategies for successful micro-architecture design, integration, verification, and post-Silicon debug. You will evaluate all chiplet integration strategies as part of your technology enablement deliverables.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Engage with industry and vendors to identify Chiplet technologies and design IPs for inhouse technology test chip development.
• Develop an overall integration plan of new technology such as D2D chiplet interface.
• Drive requirements for pre-silicon and post-silicon functional and DFT plans.
• Work with the Post-Silicon Product Engineering team on post-silicon debug.
• Execute IP sourcing, integration, to final post-silicon verification.