Design Verification Architect

Description

As a key Design Verification Architect at Arteris, you will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world's most sophisticated mobile, telecom, automotive, and consumer SoC designs.

You will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will go home at the end of the day amazed at all the places where your creations end up.

You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between - you will no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.

Key Responsibilities:

• Work with the architecture and design team to make sure the verification is taken care of as early as in the architecture stage. Work as a bridge between the architecture, the design and the verification teams.
• Guide the verification team in test plan creation, testcases, coverage and coverage exclusion.
• Provide verification methodology.

Requirements:

• Strong background in microprocessor design, cache coherency, memory ordering and cache configuration.
• Solid verification industry experience.
• Good communication skills. Good documentation skills.
• MS in EE, CS, CE or Mathematics. 10 + years' experience.

Estimated Base Salary:

• $180,000 - $280,000 annually