Design Verification Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science or equivalent practical experience.
• Experience verifying digital logic at RTL level using SystemVerilog or C/C .
• Experience creating and using verification components and environments in standard verification methodology.
• Experience verifying digital systems using standard IP components/interconnects (i.e., microprocessor cores, hierarchical memory subsystems).

Preferred qualifications:

• Master's degree in Electrical Engineering or Computer Science with 3 years of relevant experience, or PhD in Electrical Engineering or Computer Science.
• Architectural background in one or more of: Caches Hierarchies, Coherency, Memory Consistency Models, Memory Ordering, DDR/LPDDR, PCIe, Packet Processors.
• Experience with interconnect protocols (e.g., ACE, CHI, CCIX, CXL).
• Experience with performance verification of SOCs, pre-Silicon analysis and post-Silicon correlation.
• Experience with building verification methodologies that span simulation, emulation, and FPGA prototypes.

About the job

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

As a part of the Google Silicon Interconnect/Platforms team, you will work on the verification of Google's SOC offerings. You will collaborate with hardware architects and design engineers for functional and performance verification of the interconnect, cache coherency and memory consistency. You will also work on developing high performance VIPs for protocols supported by our interconnect, and closely collaborate in the deployment of the verification stack across a heterogeneous set of IPs.

Our approach to building interconnects is based on scalability. You will be verifying a generalized class of interconnects, and developing the associated methodologies and tools needed to solve the problem.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $141,000-$219,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

Responsibilities

• Plan and execute the verification of the next generation configurable interconnects and memory subsystems.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
• Develop cross-language tools and scalable verification methodologies.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.