Design Verification Engineer, Silicon

Minimum qualifications:

• Bachelor's in Electrical Engineering, Computer Engineering, or a related field or equivalent practical experience.
• 3 years of experience in silicon design verification, with a focus on SoCs or ASICs.

Preferred qualifications:

• 6 years of experience in silicon design verification, with a focus on SoCs or ASICs.
  
• Experience with scripting languages (Python, Perl) for automation.
  
• Knowledge of SystemVerilog and Verification Methodologies (UVM).
  
• Understanding of digital design fundamentals and Register-Transfer Level (RTL) coding.
  
• Familiarity with formal verification and assertion-based verification
  techniques.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Design and implement stimulus generators, monitors, checkers, and scoreboards to achieve high coverage goals.
• Utilize scripting languages (e.g., Python, Perl) for automation and analysis.
• Maintain expertise in advanced verification methodologies (e.g., formal verification, assertion-based verification).
• Utilize simulation tools (e.g., VCS, Questa), debug environments such as Verdi, and coverage analysis tools.
• Generate detailed verification reports summarizing test results, coverage metrics, and bug tracking. Create clear and concise documentation of verification environments and test procedures.