Design Verification Technical Team Lead

Company Description

Axiado is an AI-enhanced security processor company redefining the control and management of every digital system. The company was founded in 2017, and currently has 100+ employees. At Axiado, developing great technology takes more than talent: it takes amazing people who understand collaboration, respect each other, and go the extra mile to achieve exceptional results. It takes people who have the passion and desire to disrupt the status quo, deliver innovation, and change the world. If you have this type of passion, we invite you to apply for this job.

Job Description

Design Verification Technical Team Lead position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT.

You should have prior knowledge and experience with UVM verification and UVM environment development.

You will be responsible for RTL SoC/Subsystem verification of ARM based CPUs, and work on industry-standard verification methodologies like UVM, Portable Stimulus and Formal verification flows. You will report to the Director of Engineering, Verification.

KEY RESPONSIBILITIES

Project Leadership

• Drive and track testplan development and test implementation

• Technical problem solving skills

• Micro-architecture design verification, RTL verification, and documentation

• Top-level and block-level performance verification, and use-case verification and Support test program development, chip validation, and chip life until production maturity.

• Good understanding of the application of the designs at system level

Team Management and Building

• Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.

Qualifications

• 15+ years of experience in System Level verification using C and UVM verification

• Proficient in testplanning and testcase development in C/Assembly/SystemVerilog

• Expertise in verifying design at RTL level and gate-level simulation

• Good understanding of coverage analysis, performance verification and use-case verification

• Usage of the third party Verification IPs

• Experience in functional test development for post-silicon bring-up/debug

• Fluency with scripting languages (e.g., Make, Perl, Python, Shell); and

• Has worked on the project complete cycle from the Specification to Tapeout and involved in Post Silicon Validation.

• Exposure to the FPGA Validation and debug

• Expertise with PCIE, SPI/ESPI, Ethernet and internet protocols are big pluses.

ACADEMIC CREDENTIALS

• BE/BTECH or ME/MTECH degree in EE/EECS/CS or equivalent

Additional Information

Additional Information

Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent.

We are building an exceptional team to secure every node on the internet. For us, solving real-world problems takes precedence over purely theoretical problems. As a result, we prefer individuals with persistence, intelligence and high curiosity over pedigree alone. Working hard and smart, continuous learning and mutual support are all part of who we are.

Axiado is an Equal Opportunity Employer. Axiado does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need.

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