Digital ASIC Physical Design Engineer, Principal

US CITIZENSHIP REQUIRED FOR THIS POSITION: Yes

RELOCATION ASSISTANCE: Relocation assistance may be available

CLEARANCE TYPE: Secret

TRAVEL: Yes, 10% of the Time

Description

Join Northrop Grumman on our continued mission to push the boundaries of possible across land, sea, air, space, and cyberspace. Enjoy a culture where your voice is valued and start contributing to our team of passionate professionals providing real-life solutions to our world's biggest challenges. We take pride in creating purposeful work and allowing our employees to grow and achieve their goals every day by Defining Possible. With our competitive pay and comprehensive benefits, we have the right opportunities to fit your life and launch your career today.

The EDIC group delivers full-custom ICs designs to provide the core functionality of our Advanced Multifunction Sensor products. In support of that capability, we are seeking a Digital ASIC Physical Design Engineer for the physical implementation (or "back-end") of digital subcomponent blocks using automated place and route tools.

The digital content of our chips is growing so the candidate would be expected to take responsibility for the physical implementation of the digital subcomponents on an ASIC chip, working interactively with the digital RTL designer as well as the RFIC chip lead, and analog & RF designers to integrate the digital core within all aspects of the chip; including project setup, floorplan and automatic place & route scripting, DRC, LVS, STA, LEC and configuration control [primarily SVN]. Must be comfortable working in a team environment of multiple skillsets, each being accountable for their individual contribution.

The position can be filled at the T2 - Engineering Level, or T3 level - Principal Engineering Level.

Level T02; Design Engineer

Basic Qualifications:

• Typical Minimum Education or Experience 2 Years with Bachelors in Science; 0 Years with Masters
• Experience with synthesizing or using gate level logic, including compiling and placing memory macro blocks.
• Floor-planning and scripting, followed by place and route of the physical layout [full build].
• Design and planning of power and clock distribution networks, including interfacing with top-level layout/chip-lead.
• Familiarity with Cadence tools would be advantageous particularly:
  • Genus Synthesis
  • Innovus place and route
  • Virtuoso layout activities (DRC/LVS/streamIn/verilogIn/defOut)
  • Tempus Static Timing Analysis [STA]
  • Voltus power analysis
  • Conformal Logical Equivalency Checking [LEC]
• Experience with foundry approved verification tools such as Assura of Calibre for LVS/DRC
• Eligible for a Secret or higher security clearance
• s Calibre for LVS/DRC
• Eligible for a Secret or higher security clearance

Level T03; Principal Design Engineer

Basic Qualifications:

• Bachelor's degree in Electrical or Computer Engineering (other related disciplines could be considered with relevant practical experience)
• 5 years of relevant experience with B.S, 3 years with Master's, 0 years with PhD
• Experience with synthesizing or using gate level logic, including compiling and placing memory macro blocks.
• Floor-planning and scripting, followed by place and route of the physical layout [full build].
• Design and planning of power and clock distribution networks, including interfacing with top-level layout/chip-lead.
• Familiarity with Cadence tools would be advantageous particularly:
  • Genus Synthesis
  • Innovus place and route
  • Virtuoso layout activities (DRC/LVS/streamIn/verilogIn/defOut)
  • Tempus Static Timing Analysis [STA]
  • Voltus power analysis
  • Conformal Logical Equivalency Checking [LEC]
• Experience with foundry approved verification tools such as Assura of Calibre for LVS/DRC
• Eligible for a Secret or higher security clearance

Preferred Qualifications:

• Completion of the physical layout of a digital core from and RTL description
• Robust design approaches such as redundancy and Radiation Tolerance
• Experience following a rigorous design process with checkpoint reviews
• Experience in CAD design network, tool configuration, and data management
• Active Secret clearance or higher

Salary Range: $78,600.00 - $118,000.00Salary Range 2: $96,900.00 - $145,300.00

Employees may be eligible for a discretionary bonus in addition to basepay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results.Employees in Vice President or Director positions may be eligible for Long Term Incentives.In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO)for vacation and/orpersonal business.

The health and safety of our employees and their families is a top priority. The company encourages employees to remain up-to-date on their COVID-19 vaccinations. U.S. Northrop Grumman employees may be required, in the future, to be vaccinated or have an approved disability/medical or religious accommodation, pursuant to future court decisions and/or government action on the currently stayed federal contractor vaccine mandate under Executive Order 14042 https://www.saferfederalworkforce.gov/contractors/.

Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for most positions.