Digital Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The successful candidate will be a highly motivated self-starter who is able to work independently to complete assigned tasks within required project timelines with high quality. The candidate will primarily be responsible for digital RTL and behavioral coding for all IPs in the SerDes physical IP portfolio as well as executing various tool flows for IP quality control. It is also expected, however, that the successful candidate will be able to contribute hands-on technical expertise in many other phases of the digital design flow as time with the team progresses. It is further expected that the candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with design architects, project management, and digital and analog design teams in multiple worldwide geographies. Candidate should be willing to work full time in the Cary, North Carolina office and be willing to travel as required by job function (expectation is 5% travel or less).

The ideal candidate will have a fundamental understanding of the end-to-end digital design flow in order to accurately and efficiently communicate with all members of the technical staff, both analog and digital, regarding overall project development progress and status. This includes but is not limited to:

• Understanding of digital architecture trade-offs for power, performance, and area
• Understanding of proper handling of multiple asynchronous clock domains and their crossings
• Understanding of Lint checks and proper resolution of errors
• Awareness of modern digital verification flows (functional coverage closure, metric-driven verification with random stimulus, formal verification, etc) and their schedule implications
• Familiarity with synthesis flows including DFT and power management support
• Handling of low-power designs and features (power islands, state retention, etc)
• Understanding of fundamental static timing principles and constraint development
• Understanding of fundamental physical design flows and stages

Experience with Verilog coding language is desired, and the most successful candidates will be able to demonstrate excellent command of fundamental logic design principles as well as excellent problem solving and communication skills. Experience with scripting languages such as Perl, Ruby, Python, Sed, or Awk is also strongly preferred.
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