Digital Design Engineer, RTL Senior Staff II

About us:

If you are following the evolution of the leading approach in deep learning powered AI, the renaissance in NLP as well as the next disruption in computer vision, you likely know it's all about Transformer based modelsThey are powering neural nets with billions to trillions of parameters and existing silicon architectures (including the plethora of AI accelerators) are struggling to varying degrees to keep up with exploding model sizes and their performance requirements. More importantly, TCO considerations for running these models at scale are becoming a bottleneck to meet exploding demand. Hyperscalars are keen on how to gain COGS efficiencies with the trillions of AI inferences/day they are already serving, but certainly for addressing the steep demand ramp they are anticipating in the next couple of years. d-Matrix is addressing this problem head on by developing a fully digital in memory computing accelerator for AI inference that is highly optimized for the computational patterns in Transformers. The fully digital approach removes some of the difficulties of analog techniques that are most often touted in pretty much all other in-memory computing AI inference products. d-Matrix's AI inference accelerator has also been architected as a chiplet, thereby enabling both a scale-up and scale-out solution with flexible packaging options. The d-Matrix team has a stellar track record in developing and commercializing silicon at scale as senior execs at the likes of Inphi, Broadcom, and Intel. Notably, they recognized early the extremely important role of programmability and the software stack and are thoughtfully building up the team in this area even since before their Series A. The company has raised $44m in funding so far and has 70+ employees across Silicon Valley, Sydney and Bengaluru.

Location:

Hybrid, working onsite at our San Jose Headquarters 3-5 days per week with the flexibility to work remotely the remainder of your time

What you will Do:

• Responsible for the micro-architecture and design of the High-speed IO interfaces
• Own design, document, execute and deliver fully verified, high performance, area and power efficient RTL to achieve the design targets and specifications
• Design of micro-architecture and RTL, synthesis, logic and timing verification using leading edge CAD tools and semiconductor process technologies
• Design and Implement logic functions that enable efficient test and debug
• Participate in silicon bring-up and validation for blocks owned

What You Will Bring:

• BSEE 8+ years of meaningful work experience / Master's degree preferred in electrical engineering, Computer Engineering or Computer Science with 5 years of meaningful work experience
• Experience in micro-architecture and RTL development (Verilog/System Verilog), focused on Processor, Digital Signal Processing blocks.
• Exposure to Mixed-signal designs, Computer Architecture & Arithmetic is required
• Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis
• Strong interpersonal skills and an excellent teammate

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We're committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.