Digital IC Design Engineer Intern

Team info:

The Brain Interfaces SoC Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. To accelerate our pathway to human ready brain-computer interfaces, you will have the opportunity to partner with our electrical, microfabrication, chip designers, neuro and mechanical engineers.

Job Responsibilities:

We are looking for Digital IC Design Engineer Interns who are interested in architecting and implementing innovative solutions and who thrive with the autonomy to propose creative approaches to problems. 

Neuralink strives to be, as much as possible, a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals with different skill sets and perspectives, and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us.

Digital IC Design Engineer at Neuralink will own a part of the design from concept to prototype which includes

• Implementation of digital modules in RTL level in Verilog/SystemVerilog
• Functional design verification
• Board bring up and experimental design validation
• Analog mixed signal co-simulation
• Writing device drivers in C/C++

Key qualifications:

• Minimum 1 year of experience with Verilog, SystemVerilog, C, C++ 
• Minimum 3 months experience of application of technical skills outside of the classroom (examples: laboratory, research, extracurricular project teams, open source contributions, volunteering, personal projects or prior internship/work experience)
• The ideal candidates are people who get excited about building things, are highly analytical, and enjoy tackling new problems regularly.

Preferred qualifications:

• Experience working on complex digital systems, from architecture design, RTL, synthesis, verification, and place-and-route using industry standard tools.
• Experience testing and debugging digital system-on-a-chip.
• Functional modeling experience and logic verification with SystemVerilog or UVM.
• Experience designing PCBs or writing firmware.

Pay Transparency:

Based on California law, the following details are for California individuals only:

California base hourly rate: $35-$35/hr and eligible for benefits.