Director of Defect Engineering

Job Details:

Job Description:

Fab Sort Manufacturing (FSM) is responsible for the production of all Intel silicon using some of the world's most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and 2 new greenfield sites in Ohio and Germany. As part of Intel's IDM2.0 strategy, FSM is rapidly expanding its operation to deliver output for both internal and foundry customers with state-of-the-art technologies arriving in high-volume manufacturing at a 2-year cadence going forward. Intel recently created HVM Global Yield organization in FSM to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development team and FSM fab managers.

This job requisition is to seek a director level leader in FSM HVM Global Yield organization, reporting directly to VP of HVM Global Yield. The selected candidate will build and lead a team in HVM Global Yield organization and work with other leaders in the org, fab module/yield managers and TD leaders to support yield ramp-up and process optimization in early production stage, supporting internal and external customers.

Director of Defect Engineering

Responsibilities:

- Build and lead Defect Engineering team in FSM HVM Global Yield organization to execute HVM yield roadmap.

- Collaborate with Technology Development team to import new technology to production fabs across the globe.

- Work with Process Integration team, Yield Analysis team and FSM Yield managers to lead fast paced yield ramp-up in high-volume manufacturing phases.

- Identify systematic defect issues and drive mitigation actions in defined timeline to meet committed production yield targets.

- Review, compare, and propose wafer inspection tool selection options in production line with comprehensive quantitative analysis.

- Set up and optimize wafer inspection steps in process flow to ensure detection of yield detracting defects in line at step.

- Lead technical interactions with internal and external customers.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

- Bachelor's or Master's Degree in science or engineering area.

- 10+ years of experience in advanced node semiconductor industry in Defect engineering or Failure analysis.

- 5+ years of team leadership experience to manage and direct an organization of 20+ process/defect engineers in fast-paced high-volume semiconductor manufacturing environment to drive yield, technology, quality, output and cost.

- Experience in FinFET technology development or high-volume manufacturing.

- Strong understanding on defect mechanism and yield impact in semiconductor high-volume production and proven track record of driving down D0.

- Understanding on layout-sensitive defects and knowledge of scan diagnosis and other defect analysis skills.

- Working knowledge in module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology. Skills to develop improvement projects at module level to improve process for reduced defectivity and improved yield.

- Knowledge of module tool impacts to defects, inline parametrics and yield through PM life while understanding upstream and downstream impacts to other tools

- Experience in serving external Foundry customers through technical interactions.

- Problem-solving and project/program management experience with strong self-initiative and self-learning capabilities.

- Demonstrated interpersonal skills to perform at leadership role including influencing, engaging, and motivating.

- Proven track record of working across organization through matrix structures in order to accomplish strategic objectives with conflicting priorities.

- Must demonstrate strong communication skills.

Preferred Qualifications:

- Ph.D. in science or engineering area.

- Experience in GAA (Gate-All-Around) technology architecture or understanding on GAA-specific defect issues.

- Experience in new semiconductor technology development.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Arizona, Phoenix

Additional Locations:

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.