Graduate intern

Job Details:

Job Description:

Candidate will be performing lab experiments and characterizations on Cu and solder interconnects in advanced electronic packaging; Metallography sample preparation for SEM/EBSD examinations; Work with Physical Failure Analysis teams on electronic packaging interconnect failure mechanisms.

Roles and Responsibilities:

• Possess good problem-solving skills, ability to work in a dynamic and multi-functional team and the willingness to learn key concepts of microelectronic technology development.
• Experiment with various approaches involving complex datasets, create proof of concepts and prototypes of new ideas and support strategic enhancements to existing models.
• Work with Engineers from diverse engineering backgrounds to help understand interconnect failure mechanisms.
• Present and report on related technical topics.
• Excellent communication skills to both technical and non-technical audiences, including higher management, internal and external customers.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• The candidate must be pursuing a PhD degree in material sciences or related areas.
• Demonstrated Hands-on experiences with EBSD, SEM/EDS and metallography sample preparation.

Preferred Qualifications:

• Research experiences on interconnects of advance electronic packaging.

Job Type:

Student / Intern

Shift:

Shift 1 (United States of America)

Primary Location:

US, Arizona, Phoenix

Additional Locations:

US, California, Los Angeles, US, California, San Francisco, US, Connecticut, Stamford, US, Illinois, Champaign, US, Pennsylvania, Allentown, US, Pennsylvania, Lancaster, US, Pennsylvania, Philadelphia, US, Utah, Lehi, US, Wisconsin, Eau Claire

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$63,000.00-$166,000.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will require an on-site presence.