IBM Processor Architecture and Logic design : Fabric Lead

Introduction
As a Hardware Developer at IBM you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today’s market.

Your Role and Responsibilities

• As a Logic design lead in the IBM Systems division you will be responsible for the micro architecture design and development of a high-bandwidth low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems.
• Design and architect different interconnect topologies as driven by bandwidth latency and RAS requirements
• Develop the features present the proposed architecture in the High level design discussion
• Develop micro-architecture Design RTL Collaborate with the Verification DFT Physical design FW SW teams to develop the feature
• Signoff the Pre-silicon Design that meets all the functional area and timing goals
• Participate in silicon bring-up and validation of the hardware

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Required Technical and Professional Expertise

• 8 to 15 years of relevant experience
• At least 1 generation of processor interconnect design delivery leadership (eg UPI axi amba NoC).
• Expertise of SMP coherency
• Experience in different on-chip interconnect topologies (e.g. mesh crossbar)
• Understanding of various snoop and data network protocols
• Understanding of latency & bandwidth requirements and effective means of implementation
• Working knowledge of queuing theory numa/nuca architecture
• Proficient in HDLs- VHDL / Verilog
• Experience in High speed and Power efficient logic design
• Experience in working with verification validation physical design teams for design closure including test plan reviews and verification coverage
• Good understanding of Physical Design and able to collaborate with physical design team for floor planning wire layer usage and budgets placement of blocks for achieving high-performance design
• Experience in leading uarch RTL design teams for feature enhancements.
• Follow agile project leadership principles. Work with the team on estimation and execution plan.
• Ability to quickly understand issues spanning multiple functional domains switch context frequently and provide solutions to problems is necessary.

Requirements : Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance.

Preferred Technical and Professional Expertise

• None