Internship: Hardware Verification (m/w/x)

Introduction
The hardware team in Boeblingen develops the most powerful server systems in the world – in an international work environment with our partner labs in the USA Israel and India. We are using modern verification methods and are continuously optimizing our development processes.

Your Role and Responsibilities
Be part of IBM’s international hardware development team in 2025! Work on the next generation of IBM’s industry leading servers.
We can offer a variety of 3 different topics for student work (either as working student part-time for up to 12 months or as internship full-time for 6 months). Please specify in your application which topic you prefer because we would like to plan your internship according to your skills and interests. Telling us the planned duration and start date of an internship is mandatory.

Selection of possible topics:

Topic 1: Automated pre-silicon system performance analysis framework

To ensure performance targets are met before the design data of the next generation of IBM z microprocessors is sent to the fab a growing set of performance tests are performed pre-silicon in system-level simulations. However as of now the results of these tests are manually analyzed by the team of performance verification engineers.

The goal of this work topic is to develop an automation solution for the analysis of the pre-silicon system-level performance regression results. It must assist the team of performance verification engineers in finding performance issues of next-generation IBM microprocessors the most efficient way.

The work will be based on an existing rapid prototype implementation. It will re-factor improve optimize and expand it.

1. The first step would be to analyze the existing data set performance metrics and the current prototype.
2. The solution then needs to be optimized to the pre-silicon performance regression use-case e.g. by applying further data science methods and/or developing new scores.
3. Eventually AI and/or machine learning techniques can be applied to make the solution adaptive to changes throughout the project or over the course of several project respectively.

Topic 2: Enabling an open-source verification flow for IBM processors

To develop complex microprocessors multiple hierarchies of the design are being simulated in order to ensure a first-time right design when the first chips are being produced. These complex chips consisting of ASICS and processors incorporate IP as well as standard interfaces. The current IBM verification framework consists of proprietary tools from EDA vendors as well as internal tools. To enable horizontal and vertical reuse across multiple verification levels and components it is important to base the verification methodology on standards such as Portable Stimulus languages such as System Verilog but also enabling common programming languages such as Python and C++.

The goal of this work topic is to enable a verification workflow which is taking advantage of open-source developments as much as possible. One step that has already been taken is to integrate the most popular open-source verification framework CocoTB into the verification methodology. But there is much more to be enabled as part of this thesis. More specifically we would like to evaluate the capabilities of Verilator an open-source simulator https://github.com/verilator/verilator to understand how this tool can potentially augment and shape IBM’s future verification methodology.

A first step is to compare the performance of the Verilator against that of in-house simulators. Moreover – given the complexity and size of IBM hardware designs – scalability is another major factor. Based on the results and experience obtained from first test runs there are many other aspects to investigate – such as exploring if Verilator can directly be integrated into our IBM verification environments to enable SystemVerilog simulation alongside with our new designs.

If you are interested to work very close to the micro-architecture and the functionality of a design developing great user experiences for hardware development – this is the place to be!

Topic 3: Boosting simulation efficiency using container checkpointing

When developing complex microprocessors a flexible scalable and robust development environment and tools flow are of utmost importance. A variety of tools and frameworks – both from external vendors as well as internal ones – need to be run and executed across a large pool of development systems.

One of the most promising technologies in recent years has been the containerization of development environments along with the promise of massive scalability through cloud technologies such as OpenShift / Kubernetes.

First prototypes and experiments that involve the increased use of this technology for hardware development have shown promising results. The use of containers opens many possibilities that we would like to explore further.

One major part of the hardware development flow is the verification and simulation of the hardware before design data ultimately gets sent to fabrication and manufacturing. Simulation is one of the most resource intensive steps of the development flow. Any process enhancements that can be applied to this step can have a major impact on overall development flow efficiency.

The relatively new container checkpoint and restore feature (as enabled by CRIU – https://criu.org/Main_Page / “forensic container checkpointing”) promises to offer a significant performance boost for these simulation environments. While simulation relies on randomization to produce ever-changing test scenarios for most simulations there is a significant overhead introduced by the need to run an initialization sequence that is identical for all runs. Restoring the init state from a container checkpoint has the potential of removing this overhead and being a game-changer for the flow.

The objective of this work topic is to explore the capabilities of container checkpointing and to create a prototype simulation environment that can leverage this new technology. If successful there are many more use cases the simulation flow could benefit from.

IBM’s simulation framework is C++-based so a basic understanding of the language as well as container technologies is expected.
References:
https://kubernetes.io/docs/reference/node/kubelet-checkpoint-api/
https://access.redhat.com/solutions/7008477

If you are interested to work very close to the cutting edge hardware development flow and developing great user experiences for hardware development – this is the place to be!

How to apply:

If you are self-driven and enjoy a flexible and agile work environment then hardware development is your place to work. If you’re interested please get in contact with us and include in your response all relevant documents (preferably all in one single pdf file):

1) Cover Letter incl. your availability (earliest start and latest end date) and topic of choice
2) CV incl. your level of German
3) university enrollment document to prove that you are still studying
4) current transcript of records and other relevant certificates / references
5.1) Non-EU citizen studying in Germany: copy of passport residence and work permit
5.2) Non-EU citizen studying elsewhere: prove of identity incl. place of birth

Required Technical and Professional Expertise

• Study of computer science electrical engineering or a similar direction
• Good knowledge of programming (C++ preferred) knowledge of a scripting language like Python
• Knowledge of Development tools / technologies (e.g. git)
• Good team worker and interest to work in international teams
• Strong communication skills in English

Preferred Technical and Professional Expertise

• First experience in developing hardware e.g. VHDL or Verilog knowledge and performance analysis
• Knowledge of AI data science statistics and machine learning
• Knowledge of web frameworks like React FastAPI