Mixed-Signal Modeling and Verification Engineer

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Our Mixed-Signal Verification team is searching for an AMS Verification Engineer. We are looking for a strong candidate who can handle a multitude of challenges in verifying digital/mixed-signal designs. You will be at the cutting edge of high-speed communication protocols and other advanced node technologies. In this highly visible role, you will be at the center of chip design efforts collaborating with multiple teams with a critical impact on product success.

Qualifications:

• 5+ years of experience in developing and verifying real-numbered behavioral models in SystemVerilog
• Understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, and Verilog-AMS
• Basic understanding of AMS blocks like filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, Mixer, etc
• Working experience in low power Architecture
• Working experience in Cadence Virtuoso Schematic Composer and ADE
• Experience with Analog Assertion Based Verification
• Experience in TB development will be a strong plus
• Experience in writing scripts in languages such as Perl or Python
• Excellent teammate with excellent communication skills
• Experience with FPGA prototyping is a plus

Responsibilities:

• You will become part of a hands-on development team that fosters engineering excellence, creativity, and innovation.
• As an AMS Verification Engineer, you will be responsible for Developing accurate and simulation-efficient analog behavioral models for analog/RF blocks in SystemVerilog.
• Verifying that the behavior models are accurate representations of analog schematics
• Integrating the models with RTL
• Verifying analog functionalities against design specifications using analog behavioral models: for example, coding test benches, test scenarios, and assertions.
• Documenting modeling and verification results for formal review.

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