PDK Design Automation Engineer

Job Details:

Job Description:

Now is an exciting time for Intel's Design Enablement Group. This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies.

As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.

Your responsibilities will include, but are not limited to:

- The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams to develop and deliver high quality technology collaterals, models, and enablement of EDA tools.

- As PDK Validation Engineer you will support validation and release of PDK custom layout collaterals to Intel internal design and IFS customers.

- Development of automated QA flows.

- Writing efficient code in scripting languages to automatically generate, analyze large amounts of data to improve overall quality of the custom tech library released in the PDK for leading technology nodes.

- Work closely with the PDK development team and EDA suppliers to implement robust QA checks and resolve tool and collateral issues prior to PDK releases.

The ideal candidate will have the following skills:

- Written and verbal communication skills.

- Possess teamwork and problem-solving

#DesignEnablement

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum qualifications:

Candidate must possess a BS degree with 3+ years of relevant experience or MS degree with 2+ years of relevant experience in Electrical Engineering, Computer Science Engineering, or related field.

Experience in one or more of the following skills/areas:

- Cadence Virtuoso.

- Auto Place and Route.

- Perl or Python or Ruby or TCL.

- UNIX/Linux.

Preferred Qualifications:

1+ years of experience in the following:

- External EDA custom layout tools.

- Parameterized cells (Pcell).

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Arizona, Phoenix

Additional Locations:

US, California, Folsom, US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, Austin

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$119,130.00-$178,690.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.