Pervasive and Power Management Logic Design Engineer

Introduction
As a Hardware Developer at IBM you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today’s market.

Your Role and Responsibilities
As a Logic designer you will be responsible for design and development of the POR Boot Engine Boot security features and the test & debug infrastructure for very high performance Processors chips. You will be part of the design team which will deliver this critical infrastructure to IBM’s Mainframe and POWER processors.

• Develop the features present the proposed architecture in High level design discussions
• Develop micro-architecture Design RTL Collaborate with the Verification DFT Physical design FW SW teams to develop the feature
• Signoff the Pre-silicon Design that meets all the functional area and timing goals
• Participate in silicon bring-up and validation of the hardware
• Estimate the overall effort to develop the feature

#ISAISDLESD24

Required Technical and Professional Expertise
3-10 years of work experience in one or more areas:

• Architecture/ microarchitecture/ RTL Logic design of Test and Debug infrastructure for Processors/ SoCs
• Security architecture- Self Boot engine Secure boot
• Clock controllers design. Good understanding of clocks and reset architecture.
• Timing constraints timing closure. Experience as front end logic designer with sync and async timing closure for large designs working with other designers PD team.
• Experience in SPI I2C serial communication protocols. OTP on-chip sensors
• Power management Architecture/ microarchitecture/ Logic design – Dynamic power estimation Power capping droop mitigation logic development. Preferred – Prior experience with designs with multiple power states.
• Proficient in HDLs- VHDL must/ Verilog
• Experience in working with architecture/ FW/ SW teams
• Experience in low power logic design.
• Experience in working with verification validation physical design teams for design closure including test plan reviews and verification coverage
• Good understanding of Physical Design and able to collaborate with physical design team for floor-planning placement of blocks for achieving high-performance design

Preferred Technical and Professional Expertise

• None