Physical Design Engineer, Senior Staff

About us:

If you are following the evolution of the leading approach in deep learning powered AI, the renaissance in NLP as well as the next disruption in computer vision, you likely know it's all about Transformer based modelsThey are powering neural nets with billions to trillions of parameters and existing silicon architectures (including the plethora of AI accelerators) are struggling to varying degrees to keep up with exploding model sizes and their performance requirements. More importantly, TCO considerations for running these models at scale are becoming a bottleneck to meet exploding demand. Hyperscalars are keen on how to gain COGS efficiencies with the trillions of AI inferences/day they are already serving, but certainly for addressing the steep demand ramp they are anticipating in the next couple of years. d-Matrix is addressing this problem head on by developing a fully digital in memory computing accelerator for AI inference that is highly optimized for the computational patterns in Transformers. The fully digital approach removes some of the difficulties of analog techniques that are most often touted in pretty much all other in-memory computing AI inference products. d-Matrix's AI inference accelerator has also been architected as a chiplet, thereby enabling both a scale-up and scale-out solution with flexible packaging options.

The d-Matrix team has a stellar track record in developing and commercializing silicon at scale as senior execs at the likes of Inphi, Broadcom, and Intel. Notably, they recognized early the extremely important role of programmability and the software stack and are thoughtfully building up the team in this area even since before their Series A. The company has raised $44m in funding so far and has 70+ employees across Silicon Valley, Sydney and Bengaluru.

Location:

Hybrid, working onsite at our San Jose Headquarters 3-5 days per week with the flexibility to work remotely the remainder of your time

What you will Do:

The candidate will be responsible for the 7nm high speed physical designs and working with a 3rd party design services to implement and verify. You will be directly involved in:

• Methodology & Flow development of Physical Design and Timing Closure for custom and semi-custom blocks.
• Floorplanning including multi-power domain, PG planning etc
• Physical implementation of blocks and top-level including clock-tree.
• Physical verification, Timing closure and Formal verification for blocks and top-level.
• Static and dynamic IR drop analysis, signal, and power EM checks.
• Interfacing with internal and external teams including Design, IP, Library.
• Interfacing with 3rd party Design Services company to ensure physical design achieves the best QoR

What You Will Bring:

MS in EE/CS with 8-10 years of previous experience.

Exposure on ASIC design, layout and semiconductor device/process through previous work/intern experience or course work.

Experience with scripting/programming using Tcl/Tk/Perl.

Detail oriented, self-motivated team worker, good verbal and written communication skills.

Previous experience on physical design and automatic place and route a plus. i.e., Knowledge of Synopsys/Cadence P&R tools.

Previous experience on custom layout and physical verification a plus.

Previous experience on synthesis/STA/FV a plus.

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We're committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.