Principal Application Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for an Application Engineer System Verification, based in Grenoble or Paris-Velizy  

Job purpose:

The successful candidate will be expected to work independently and in collaboration with other team members to resolve customer issues, support technology adoption and identify opportunities and risks associated with those activities. The AE will liaise with the R&D and Marketing organizations to communicate customer requirements, influence product direction and validate solutions.

The AE will work closely with the Sales team to support technical sales campaigns and develop the skills needed to demonstrate and adapt solutions to meet customer requirements. The AE will also develop the ability to deliver training courses and workshops covering the Functional Verification Platforms and over time mature into a strong team member and become a key contributor, leading projects and initiatives. The position will include travel to customer sites and involve significant interaction with customers.

Responsibilities:

Provide direct technical pre- and post-sales support for Cadence Verification products, in the context of a solid technical understanding of the complete verification flow:

• Take part in technical campaigns to enable our customers to adopt Cadence Technology
• Build understanding of the customer’s needs, work closely with sales to define and adapt strategy.
• Manage customer evaluations/benchmarks, establish technology differentiation and leverage Cadence competitive advantages.
• Perform methodology assessments, improve design and verification methodologies leveraging Cadence technology and services.
• Assist customers in adopting and use Cadence technology by providing verification methodology and tool knowledge.
• Drive best practices delivering trainings, workshops and support in tool usage to establish trusted relationship and credibility.
• Interact closely with Cadence R&D (Product Engineers and R&D Engineers) to feedback customer needs.

Requirements:

The candidate should have:

• Master Eng in Electronic / Micro-Electronic Engineering or equivalent
• 5 to 8 years of experience in hands-on Verification.
• Experience of Hardware Design and Verification languages including Verilog, VHDL System Verilog and UVM
• This job position requires a good understanding of:
  • Common verification flows and methodologies such as UVM, Coverage-Driven Verification, Assertion-based Verification, Low-Power Verification and Software Driven Verification
  • Experience and knowledge of protocols like AMBA, Ethernet, USB, PCIe, MIPI (Not require all)
  • Experience with Unix / Linux environment including scripting languages
• Of advantage would be:
  • Experience in Hardware emulation or prototyping
  • Digital Mixed signal simulation using real modeling
  • Experience in Formal property checking (PSL or SVA)
  • Knowledge in one or more of the following Languages in the context of Design & Verification: UPF, C / C++ / System-C / TLM / Specman e
  • Familiar with the full SoC design flow
• Excellent problem-solving skills and good presentation and communication skills are a must
• Team orientation, mature work attitude, and good judgment under pressure
• Ability to travel in Southern Europe and world-wide
• Fluent in English and in French, excellent level in both languages.

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