Principal Application Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop innovators and leaders who want to make an impact on the world of technology.

We offer amazing opportunities to grow, no matter where you are in your career. The ideal candidate will be energetic, innovative and enthusiastic about how to help customers solve their toughest verification problems using Cadence technology. Join our elite application engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces™ year after year!

As an integral member of the North America Verification Field Applications Engineering (AE) Team, you will work directly with industry leading semiconductor and system companies to deploy Cadence’s market leading verification platforms including cutting edge technologies as Portable Stimulus Standard and machine learning. In this customer facing role you will provide the front line technical support in the pre and post-sales process and will work with the account team to come up with innovative solutions to address our customers’ most challenging problems in verification. You will own customer success!

In this role, you will develop customer specific verification requirements, including advanced verification component development, methodology support, and operation and maintenance of Cadence’s verification tools and services. You will support technical evaluations and benchmark development for Cadence’s market leading tools such as Xcelium simulation platform, vManager verification management platform, Perspec portable stimulus system and our vast VIP portfolio. You will create and conduct technical presentations and product demonstrations for customers.

At Cadence, customers are at the heart of everything we do. Talented engineers like you are what enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in verification tools, unlock unique expertise in verification methodologies, and level up your communication, customer, and sales skills. No matter where you are in your career, whether your next career step is to stay on the technical track, move up in management, or explore sales/marketing career opportunities, the skills and expertise you gain as an Application Engineer here at Cadence will put you miles ahead in your career advancement.

Minimum:

BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field

Experience with SystemVerilog, VHDL, Verilog

Verification skills such as UVM testbench architecture, development and debug

Strong RTL and Testbench debug skills

Experience in writing scripts (Perl, Python or Tcl)

Strong software, HDL design and verification skills

Ability to quickly analyze verification environments and design complexity

Strong verbal and written communication skills

Strong teamwork skills

Ability to interact effectively with both external customers and R&D teams

Preferred:

Experience with C/C++/SystemC

Experience in deploying VIP in testbenches

Knowledge of protocols like JTAG, UART, PCIe, AMBA, DDR

Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing

Digital design experience

Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support

In collaboration with R&D, provide in-depth technical assistance to help support advanced verification flows to secure design wins

Champion the customer needs and work closely with R&D and marketing to develop competitive and creative technical solutions

Understand the competitive landscape and continuously work on differentiating Cadence’s solutions

Write technical product literature such as application notes and technical articles

Review new product proposals and device specifications

Assume technical leadership roles in small roles in small teams as needed

Minimum:

BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field

5+ years experience with SystemVerilog, VHDL, Verilog

Verification skills such as UVM testbench architecture, development and debug

Strong RTL and Testbench debug skills

Experience in writing scripts (Perl, Python or Tcl)

Strong software, HDL design and verification skills

Ability to quickly analyze verification environments and design complexity

Strong verbal and written communication skills

Strong teamwork skills

Ability to interact effectively with both external customers and R&D teams

Preferred:

Experience with C/C++/SystemC

Experience in deploying VIP in testbenches

Knowledge of protocols like JTAG, UART, PCIe, AMBA, DDR

Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing

Digital design experience

The annual salary range for California is $120,400 to $223,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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