Principal Design Engineer

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Principal Design Engineer

The Principal Design Engineer responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.

Job Description

• Candidate's background should include a minimum of 5-10 years of experience in CMOS SerDes or high-speed I/O IC design and development
• Working knowledge of a set of common SerDes standards and their electrical requirements
• Must have a thorough understanding of jitter and signal equalization techniques
• Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; Bias and Bandgap; and Voltage Regulators
• Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment

Position requires

Proficiency in using CAD tools for circuit simulation, layout, and physical verification

• Cadence tool experience, lab test experience, and design experience at >10Gbps and in < 28nm technologies are a plus
• MSEE or PhD. EE

As a condition of employment with Cadence, newly hired employees will be required to provide Cadence with proof of full vaccination, unless legally entitled to an accommodation.

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