Principal Physical Design Engineer (PNR/Physical Verification/STA/EMIR)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.

Job Description

- Physical Design, including: floorplan, placement, CTS, routing, etc.

- Physical Verification

- Static Timing Analysis

- EM/IR Analysis

Job Qualification:

- Extensive knowledge of the design rule for the process of N7/N5 and below

- Knowledge of scripting languages and use in methodology

- Ability of fixing the physical design violations, including: DRC, DFM, LVS, ANT, ERC etc.

- Deep experience of static timing analysis

- Bachelor or above degree in majors of EE/CS/IT, with more than 12 years' work experience

- Ability to learn quickly

- High level of communication and teamwork

- Carefulness, responsibility and persistence

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