Principal/Senior Design Verification Engineer

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Allegro Microsystems is a world leader sensor company for mixed-signal sensor designs. Our sensors main applications are within traditional IC engine and self-driven electric automotive, consumer electronics, green energy industry, data center servers and industrial solutions. We are working with our partners to provide key solutions in growing new wave of applications that are at the center of self-driven cars, robotics and drone technologies.

Primary focus for this job position is verification of mixed-signal sensors with Universal Verification Methodology (UVM - SystemVerilog). You will be involved with leading projects from feasibility to tape out. As an integral part of the product development team, you will be exposed to variety of advanced tools based on specific application requirement. This includes Mathwork's Simulink and Matlab scripting, programming in C for embedded processors.

Job Responsibilities:

• Lead Digital and Digital Mixed Signal verification effort at the system level.
• Work with system architects and create accurate design reference model.
• Create verification plan and model system from design requirements/specification based on various sources including systems engineering specs, marketing documents, existing design specs.
• Use constrained random test benches and tests and assertion checkers using UVM and SystemVerilog.
• Work on fault campaign on the design to fulfill ISO 26262 requirements on functional safety.
• May use MBSE (model based system engineering) strategies to verify and validate the digital system for mixed-signal sensor using Simulink V&V toolset and test harnesses.
• Script generation for model/test configuration as well as for processing results.
• Consult with design engineers on design for testability and coverage enhancement.

Skills and Qualifications:

• BS or MS Degree in Electrical Engineering or affiliated disciplines.
• Candidate must have at least 3 to 5 years of direct design verification experience for Senior level position. And, around 10 years of relevant experience needed for Principal level.
• Excellent communication, problem-solving and lab debug experience is required.
• Experience with Verilog, SystemVerilog, UVM, lab prototyping and FPGA design and implementation.
• Experience with Matlab and Simulink toolset is a strong plus.
• Exposure to a higher-level object-oriented language is highly desired (C++, Python, etc.).
• This role is open to someone who is willing to relocate to the Manchester, NH or Texas area and work in a hybrid capacity or work remotely(in some exceptional case).

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At Allegro, we are committed to providing a harassment-free environment of mutual respect to fuel innovation through inclusive thought collaboration. Allegro is an Equal Opportunity Employer and does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, national origin, veteran status, parental status, or any other basis covered by appropriate law. Allegro makes hiring decisions based solely on qualifications, merit, and business needs at the time.