RTL Design and Verification Engineer
Job Description
Job Description:
RTL Design and Verification engineering College Graduate position is available within the Intel Data Center Power Solution group. The Power Solutions group works with Intel silicon, package, and board design teams to deliver leading edge power solutions. The successful candidate will be a key contributor to the pre-silicon functional verification of state-of-the-art power management ICs.
Your responsibilities will include but not be limited to:
- RTL design with experience leading implementation of controller for power management ICs
- Design and Pre-Si verification with experience leading Verilog RTL and model development, prefer experience working with PMIC (Power Management IC's)
- Pre-Si digital verification of power management ICs at system level in emulation
- Root causing of reported power control issues including RTL implementation, analog models, and specification errors
- Writing verification plans and documenting models, test benches.
- Writing and maintaining behavioral models, test benches, and test cases in SystemVerilog
- Leading external suppliers through development of the power management IC RTL
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordingly.
Minimum qualifications:
- Master's or PhD degree Electrical Engineering, Computer Engineering or related field.
6+ months of experience or course work in:
- VLSI Design and Architecture
- Digital Systems and Circuits
- Hardware Design Lang/Prog Logic
Preferred Qualifications:
1+ years of experience or coursework in:
- Functional design verification for power management applications
- RTL design and coding expertise using Verilog and/or VHDL for verification and testing digital circuits
- Power management IC's
- I2C, I3C, and PMBus bus protocol
- Creating and evaluating synthesis/build and simulation tool flows
- Digital design and Pre-Si verification of mixed-signal systems, specifically PMICs
- Developing synthesizable analog behavioral models representing PMIC behavior in Pre-Si SOC/ASIC environments
Job Type:
College Grad
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Business group:
The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies-spanning software, processors, storage, I/O, and networking solutions-that fuel cloud, communications, enterprise, and government data centers around the world.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Date Posted
05/10/2023
Views
22
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