Senior DFT Engineer (Design For Test)

As an Astera Labs’ Senior DFT (Design For Test) Engineer, you will be part of the DFT Design team that develops the next generation of Astera Labs’ connectivity products that support the world’s leading cloud service providers and server and networking OEMs. In this role, you will have exposure to the full product life-cycle, from definition to mass production to end of life of the products. You will be working closely with all engineering teams, physical design and functions like back-end testing, manufacturing, defect, and reliability analysis. This employee must be team oriented with a focus on solving problems in a collaborative manner between multiple engineering teams.

Basic qualifications:

• Bachelor’s degree in Computer Engineering/Electrical Engineering
• 5+ years of experience in a semiconductor company as a DFT engineer

Required experience:

• Chip design, Verilog and System Verilog
• Verification, UVM methodology
• ATPG tools
• Scan insertion tools
• Gate-level simulations
• Static timing analysis
• Scripting (Perl/Tcl)
• Familiarity with ATE
• Hands-on expertise with commercial test generation tools for large complex designs
• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression
• Experience running test compression software
• Experience using the Mentor Tessent or synopsys DFT Max and Tetramax tools

Preferred experience:

• Experience with defining and implementing SOC level verification on large designs.
• Working with 93k Tester
• Experience with IEEE 1500 Standard or IEEE 1687 standard and MBIST, LBIST

The base salary range is $120,000.00 – $170,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.