Senior Digital Design Engineer (FPGA/ASIC)

About Paradromics

Brain-related illness is one of the last great frontiers in medicine not because the brain is unknowable but because it has been inaccessible. Paradromics is building a brain-computer interface (BCI) platform that records brain activity at the highest possible resolution: the individual neuron. AI algorithms then decode this massive amount of brain-data enabling the seamless translation of thought into treatments. 

Our first clinical application the Connexus® BCI will help people who are unable to speak due to ALS spinal cord injuries and stroke to communicate independently through digital devices. However the capabilities of our BCI platform go far beyond our first application. With the brain in direct communication with digital devices we can leverage technology to transform how we treat conditions ranging from sensory and motor deficits to untreatable mental illness.
The Role

As a Senior Digital Design Engineer you will translate algorithms and system requirements into clear digital microarchitectures and high-quality synthesizable RTL that forms the foundation of our silicon. You will own digital blocks from microarchitecture through RTL implementation and work closely with physical design across the RTL-to-GDS flow to deliver robust production-quality designs using implementation feedback to drive architecture and algorithm tradeoffs for best PPA.

Rapid FPGA prototyping is a core part of this role: you will bring designs up early on FPGA to de-risk architectures validate interfaces and enable system-level integration and lab testing. You will own FPGA implementation end-to-end (synthesis constraints implementation and timing closure) iterating quickly while keeping a clear eye on how designs will translate cleanly from FPGA to ASIC.

• Define digital microarchitecture for datapaths control buffering and interfaces.
• Write high-quality synthesizable RTL for FPGAs and ASICs.
• Own FPGA implementation end-to-end: synthesis timing/physical constraints implementation timing closure and board-level debug.
• Translate DSP algorithms into efficient real-time hardware pipelines.
• Produce clear interface specs block diagrams and timing documentation.
• Partner with physical design to refine RTL and microarchitecture based on synthesis and timing feedback.
• Contribute to verification planning and debug using waveforms logs and assertions.
• Support front-end checks (lint CDC/RDC constraint reviews).

Master’s or Ph.D. in Electrical Engineering Computer Engineering or equivalent experience.

• 5+ years designing RTL for FPGAs and/or ASICs including microarchitecture and ownership of a major block from spec to signoff.
• Deep proficiency in SystemVerilog/Verilog (or VHDL) for synthesizable RTL.
• Strong theoretical foundation in digital signal processing (i.e. filters transforms and sampling). 
• Strong hands-on FPGA prototyping and bring-up experience (constraints implementation timing analysis board debug).
• Experience translating DSP algorithms into efficient real-time hardware pipelines.
• Experience with digital control of analog/mixed-signal IP including ADC/DAC control SPI/I²C high-speed SERDES and clocking/reset logic.
• Proven ability to develop microarchitecture from system requirements.
• Understanding of process-node tradeoffs and their impact on RTL and microarchitecture.
• Familiarity with front-end flows (synthesis STA lint CDC/RDC).
• Strong debug skills using waveforms logs and implementation reports.
• Scripting in Python/Tcl/Perl for automation and analysis.

• Experience proactively tuning RTL and microarchitecture to deliver ASIC-ready RTL that meets PPA targets in collaboration with physical design.
• Familiarity with SystemC or high-level behavioral modeling.
• Exposure to UVM/formal and SystemVerilog Assertions (SVA).
• Working knowledge of DFT (scan MBIST/LBIST).
• Experience with common interfaces (AXI/APB SPI I²C UART).
• Experience with silicon debug.
• Familiarity with neural signal processing or real-time data systems.

What We Do

ENABLING NEUROTECHNOLOGY Paradromics’ Brain-Computer Interface (BCI) platform records brain activity at the highest possible resolution: the individual neuron. Our AI algorithms decode this massive amount of brain-data enabling the seamless translation of thought into treatments. THE MISSION Data-driven BCI-based technologies for brain health Our technology will help millions with unmet medical needs suffering from paralysis and movement disorders to chronic pain addiction depression and other mental health conditions. ABOUT Matt Angle Ph.D. (CEO) founded Paradromics to build a high-data-rate BCI platform capable of addressing critical unmet clinical needs. With early funding from the NIH and DARPA the company developed its core neurotechnology and by 2019 shifted focus to its first product: the Connexus® BCI. Connexus is designed to restore communication through text synthesized speech and computer control for people with severe motor impairments including those caused by ALS stroke or spinal cord injury. Backed by two FDA Breakthrough Device Designations and a successful first-in-human recording in May 2025 Paradromics is now preparing to launch a clinical trial in late 2025 to evaluate the long-term safety and participant benefits of their first product the Connexus BCI.