Senior Engineer I - Verification

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Job Description:

The successful candidate will be responsible for the Verification of Microchip’s high performance Digital Signal Controller families

Job responsibilities:

• Perform design verification of complex digital macros at the SOC level, working from an architectural description
• Develop an effective suite of tests and testbench environment using VMM/UVM/System Verilog based verification
• Perform RTL, Gate level verification of 16-bit Microcontroller products
• Develop Functional safety tests, fault injection simulations & coverage analysis 
• Debug complex issues at full chip level
• Participate in a global team setting on the development of advanced microcontroller products

Requirements/Qualifications:

Qualification:

• Bachelor’s degree or higher with Electronics in your course work
• 3 - 6 years of functional verification experience in complex IP/SubSystem/SoCs in RTL and Gate level.
• Hands-on experience using an industry-standard verification methodology (UVM/VMM).
• Hands-on experience on System Verilog
• Experience writing and debugging SystemVerilog Assertions (SVAs).
• Ability to understand project specifications and come up with a comprehensive set of requirements and develop a verification test plan.
• Good understanding of digital design fundamentals.
• Good Understanding of Functional safety, fault injection simulation and coverage analysis.
• Knowledge of Unix/Linux based systems as well as scripting languages like Perl/python is an added advantage
• Understanding of Microcontroller architectures and products is a plus

Travel Time:

0% - 25%