Senior Engineer II-Design

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

Microchip’s Data Center Solutions (DCS) Business Unit offers industry leading performance, reliability, and security for PCIe Switches, and NVME Controllers. As a Principal Engineer-Design, you will provide leadership in the highly successful PCIe Switch product line. These complex 800M gate+ integrated silicon devices enable top tier data centers in next gen storage, artificial intelligence and automotive market segments.

As a Senior Engineer II-Design, your job will entail the following:

• Defining verification plans and building verification environments for chip/module level designs using System Verilog with UVM.
• Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.
• Simulations using Cadence Incisive Enterprise Simulator, and debugging using SimVision.
• Writing test cases, checkers and coverage that implement the verification test plan.
• Support emulation, ASIC lab validation including lab debug and providing root-cause simulations and workarounds.

Requirements/Qualifications:

• Minimum BSEE and of 8 years related proven verification or silicon design experience
• RTL verification using coverage driven verification techniques
• Scripting in any language
• Proficient in HDL languages SystemVerilog, Verilog or VHDL
• Familiarity with UNIX environment
• Good analytical, oral and written communication skills
• Able to write clean, readable, and maintainable code
• Self-motivated, proactive team player
• Beneficial Experience
• Programming experience or coursework in C, C++
• Experience or academic knowledge of the design and verification of interfaces and controllers for high speed serial protocols such as Serial Attached SCSI, Serial ATA, and PCI-Express
• Understanding of ASIC designs and verification methodologies
• Knowledge of MIPS or ARM, X86 system architecture

Travel Time:

0% - 25%

Physical Attributes:

Hearing, Other, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements:

100% inside, 80% sitting, 10% standing, 10% walking

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations, please refer to the EEO is the Law Poster and the EEO is the Law Poster Supplement. Please also refer to the Pay Transparency Policy Statement.