Senior Engineer II - Software

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.

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Job Description:

Microchip’s FPGA software engineering team develops the Electronic Design Automation (EDA) software used by our customers to program Microchip FPGAs. Customers perform their entire FPGA design flow using our software: from design entry, to synthesis, through place-and-route, timing, power analysis, and simulation.

The High-Level Synthesis (HLS) software engineering group develops Microchip’s high-level synthesis integrated development environment. High-level synthesis allows our customers to program FPGAs using the C/C++ software language. Customers who program FPGAs using the C/C++ language are significantly more productive because C/C++ has a higher level of abstraction than traditional low-level FPGA languages like Verilog/VHDL. Customers achieve shorter design times, easier verification, and faster time-to-market using high-level synthesis.

As a software engineer in the High-Level Synthesis group, you will work on cutting-edge high-level synthesis compiler software with a team of industry-leading experts. You will be joining an agile fast-paced engineering team, where you will solve highly challenging yet interesting problems. You will have ownership over meaningful new software projects from inception to development, testing, writing user documentation, and releasing to Microchip FPGA customers.

Responsibilities:

• Contribute to our state-of-the-art high-level synthesis compiler to generate high-performance FPGA hardware from a C/C++ algorithmic description.
• Our high-level synthesis software is built on the open-source LLVM compiler infrastructure. You will develop and improve LLVM compiler transformation and analysis passes for targeting FPGAs.
• Optimize the HLS-generated hardware architecture to improve the quality of the generated hardware circuit (Fmax and area).
• Investigate complex real-life customer applications designed with high-level synthesis to optimize performance/area and implement new HLS features as required.
• Design HLS-optimized libraries for computer vision (OpenCV), math functions, machine learning, and digital signal processing filters.
• Provide technical leadership and mentorship to junior developers.
• Participate in code reviews, design discussions, and contribute to the overall software development process.

Requirements/Qualifications:

Minimum Qualifications:

• BS, MS or PhD Degree in computer science or electrical/computer engineering.
• 10+ years of Software Engineering experience with a focus on digital design and EDA tools.
• Excellent programming skills. Proficient in C/C++.
• Strong knowledge of compilers. 5+ years of experience in working with LLVM, strong knowledge of its internals.
• Strong knowledge of algorithms and data structures.
• Solid understanding of digital design principles, including RTL design, synthesis, and verification.
• Familiarity with hardware description languages (HDLs) such as Verilog, VHDL, or SystemVerilog.
• Excellent problem-solving skills.
• Strong communication skills and the ability to articulate complex technical concepts.

Preferred Qualifications:

• Experience working with the MLIR is a definite plus.
• Strong knowledge of digital design and in-depth working experience with FPGAs. Exposure to high-level synthesis tools.
• Experience with Git source code version control.
• Experience with shell scripting languages (Perl, Python, Bash, TCL).
• Comfortable with large-scale software development in both Linux and Windows environments.

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