Senior Firmware Engineer – DDR

Job Description:

As an Astera Labs Senior Firmware Engineer, you will be designing and developing Firmware for enabling technologies like DDR and/or CXL/PCIe for future-looking products defined by Astera Labs CXL solutions.

Basic qualifications:

• Bachelor’s in electrical engineering / Electronics / Computer Science or related fields.

Required experience:

• 2-5 years of experience in developing Firmware using C in Embedded environments.
• Good knowledge of DDR training and/or DDR controller features including Memory RAS -or-
• Good knowledge of PCIe devices at PHY/Link/Transaction levels
• Ability to design, implement, and write unit-level tests for DDR or PCIe features.

Preferred experience:

• Post-silicon bring-up and validation of DDR memory or PCIe/CXL interfaces.
• Experience in advanced features of DDR like ECS/PPR/Chip Kill -or-
• Experience in debugging PCIe/CXL link issues, PCIe device configuration and error handling
• Knowledge of Server memory performance tuning for latency and bandwidth 

The base salary range is USD 120,000.00 – USD 170,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.