Senior Layout Engineer - Integrated Photonics

We are looking for a Senior Layout Engineer, Integrated Photonics. As a Senior Layout Engineer, you’ll be part of a cross-functional team whose mission is to lead IonQ on its journey to build the world’s best quantum computers to solve the world’s most complex problems. In this role, you will focus primarily on layout of masks for micro and nanofabrication of photonic integrated circuits (PICs), as well as chip-scale ion trap circuits, for use in trapped-ion quantum computer systems.  In addition to performing any required manual layout, you will help develop and maintain the internal component PCell and circuit layout libraries, as well as write scripts to automate the layout of masks for tapeouts. In this role you will also have the opportunity to work closely with the PIC and ion trap design and testing teams to help develop new and game-changing quantum technology to enable scalable quantum computing.

Responsibilities:

• Conduct layout for PICs and chip-scale ion trap circuits
• Develop and maintain internal component PCell and circuit layout libraries
• Develop and maintain scripts supporting the automated chip layout pipeline
• Develop and maintain scripts interfacing with simulation pipeline and testing pipeline 
• Ensure high quality, scalable, well-tested scripts through code architecture, code reviews and version control
• Build robust and well-engineered software solutions
• Effectively self-manage projects, priorities, deadlines, and deliverables
• Create clear and concise documentation of your layout designs and other work
• Identify, track and mitigate execution roadblocks and technical risk
• Provide clear, concise communication to management and team members

You’d be a good fit with: 

• Bachelor’s degree in Integrated Photonics, Electrical Engineering, Computer Science, or related field, or equivalent practical experience
• Experience performing layout for large-scale photonic integrated circuits and/or large-scale electronic-photonic integrated circuits
• Experience using professional layout EDA tools such as Cadence, Luceda, Synopsys, Siemens, etc.
• Proficiency in physical verification including DRC, LVS, and ERC.
• 3+ years programming experience in a general-purpose programming language (like Python or C++)
• 2+ years industry experience in chip layout projects
• Proven ability to estimate required time to complete mask layout and to meet rigid mask tapeout deadlines
• Expert skills using scripting languages to automate mask layout via commercial or open source layout software
• Experience working with other technical experts, particularly software engineers and chip design engineers
• Basic knowledge of typical micro or nanofabrication processes and their achievable critical dimensions
• Experience collaborating with commercial foundries to deliver layouts that satisfy design rules

You’d be a great fit with: 

• MS in Integrated Photonics, Electrical Engineering, Computer Science, or a related degree
• 5+ years industry experience in chip layout projects
• Expert skills using scripting languages via layout packages developed for photonics: Luceda IPKISS, Cadence Virtuoso, or similar software packages