Senior Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
 
The Cadence Advantage
• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.
 
Job responsibilities:
BE/BTECH/ME/MTECH Or Equivalent Degree 8+ to 15years

RESPONSIBILITIES:
- Develop test plans, tests, and verification infrastructure for complex IP’s/sub-system/SOC’s.
- Create verification environment using UVM methodology or equivalent.
- Build reusable bus functional models, monitors, checkers, and scoreboards.
- Drive verification closure through functional coverage.

SKILL SETS:
- BTech/ MTech in Engineering
- 5-13 years of VLSI industry experience in Verification.
- Proficiency in DDR Protocol (DDR5, LPDDR5/USB) and USB3 protocol.
- Expertise in IP/Sub_System/SoC level verification.
- Strong in developing test bench/test cases using SV & UVM.
- Experience in verification cycle for complex IP/SOC projects.
- Familiarity with code coverage, functional coverage & assertions.
- Knowledge of bus protocols (AXI/AHB/APB).

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