Senior Principal Design Verification Engineer - DDR

We are looking for Senior Principal Design Verification Engineers with proven experience in working on industry-standard protocols such as DDR or CXL/PCIe. Using your coding and protocol expertise, you will contribute to the functional verification of the designs from coming up with block-level and system-level verification plans to writing test sequences, test execution, collecting and closing coverage.

Basic qualifications

• Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE is required and a Masters is preferred.
• ≥12 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.
• Knowledge of industry-standard simulators, revision control systems, and regression systems.
• Entrepreneurial, open-minded behavior, and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience with working on DDR controller and DDR PHY IP. Solid understanding of protocol training and DRAM JEDEC standards is a must.
• Experience with interpreting industry-standard protocol specifications to come up with verification plans and execute them in simulation and emulation environments.
• Must be able to work independently to develop test plans, and related test sequences in UVM to generate stimuli and work collaboratively with RTL designers to debug failures.
• Develop user-controlled random constraints in transaction-based verification methodology. Experience writing assertions, cover properties, and analyzing coverage data.
• Must have prior experience using Verification IPs from 3rd party vendors for DDR4/5 standards.

Preferred Experience

• Prior experience bringing up DDR4/5 in the lab is a plus
• Experience in verifying performance/error-injection/timing-configurations
• Familiar with VIP integration and testing at block level and system level

The base salary range is USD 184,000.00 – USD 270,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.