Senior RTL Design Engineer (eInfochips)

Position:
Senior RTL Design Engineer (eInfochips)
Job Description:
Qualifications:• 7+ years of related technical engineering experience• 5+ years of experience applying digital design principles in SoC and/or IP development.• Proficient in Verilog/System Verilog coding constructs.• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)• Experience with high speed PCIe designs and protocols.• Experience with Industry standard interface protocols such as AXI, APB, etc.• Experience with ARM Fabric IPs.• Experience with IPXACT.• Understanding of Computer Architecture fundamentals.• Ability to write scripts using Python, Tcl, Perl etc.• Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.• Proficiency with UPF (Low power intent)• Proficiency in clock crossing techniques.• Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
Education:
Bachelor's / Masters
Annual Hiring Range/Hourly Rate:
Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer.

Location:
US-CA-California (Remote Employees)
Remote work employees may be required to be present at the closest designated Arrow office for work-related purposes, at the Company's request and sole discretion.
Time Type:
Full time
Job Category:
Engineering Services
EEO Statement:
Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)