Silicon DD Engineer

Fresh Consulting is a design-led, software development and hardware engineering company, offering end-to-end digital services to help companies innovate. We bring together amazing UX designers, sophisticated developers, digital strategists, and top-notch engineers to help companies create fresh experiences that connect humans, systems, and machines. We’ve been growing fast and need someone to help us continue to manage the delivery of high-quality work in a fast-paced environment. 
See more at freshconsulting.com Visit freshconsulting.com/portfolio to see our project work across several industries.
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Title: Silicon DD Engineer
Duration: 1 year with possible extension 
Location: Redmond, WA
Benefits: Employee benefits at 100% including Medical, PTO, Holiday Pay, 401K Plan, and much more!
Hours: Minimum 40 Hours/Week 
Role:
- Contribute to the development of efficient µArchitectures and contribute to ASIC digital µArchitecture, design and verification.
- IP integration.
- Understand Design for Verification concepts.
- Drive the top-level µArchitecture definition and develop the necessary RTL.
- Drive the chip-level integration, verification plan development, and verification.
- Supervise the RTL-to-GDS flow and assist with synthesis and timing closure.
- Support the test program development, chip validation, and chip life until production maturity.
- Work with FPGA engineers to perform early prototyping.
- Support hand-off and integration of blocks into larger SOC environments.
- Assist with Algorithm analysis, verification and improvement.
- Contribute to ASIC digital architecture, design and verification.
Skills:
- 5+ years of FPGA design experience using Verilog, and, SystemVerilog.
- 5+ years of experience in AMD/Xilinx FPGA design. (Kintex/Virtex UltraScale+ desired, 7-series minimum)
- 4+ years of experience as a Digital Design Engineer and/or a Chip Lead.
- Experience in RTL coding, synthesis and/or SoC Integration.
- Experience in digital design µArchitecture.
- Experience with UPF-based simulation flow.
- System Verilog OVM/UVM experience.
- Tcl and Python (or similar) scripting experience.
- Experience in SoC integration and ASIC architecture.
Education: BSCSE or related.
FRESH--
- Work on engineering and research assignments with F500 companies and startups.
- The relationships that we have created with our clients are one of a kind.
- We help solve problems in many technologies focusing on R&D, product development, and manufacturing.
- We work with the most cutting-edge and latest technologies from AR/VR to Autonomous technologies.
- Closely working with our clients, we believe that long-term investments are extremely important to maintain the culture we together have created.
We’re a handpicked team of Engineers, digital strategist, designers, and developers united together in creating a fresh experience. Whether we are strategizing, designing, developing, or analyzing, our integrated team works as an extension of yours to improve your impact, your usability, and your customer conversion. In the process, we collaborate with you to get to know your business, understand your industry, and incorporate your big ideas into memorable experiences that keep your customers coming back for more.
Equal employment opportunity: All qualified persons will be considered for employment without regard to race, color, religion, sex, national origin, age, marital status, familial status, gender identity, sexual orientation, disability for which a reasonable accommodation can be made or any other status protected by law. Assistance will be gladly provided upon request for any applicant with sensory or non-sensory disabilities.
Fresh Consulting is a participating E-Verify company.
freshconsulting.com
Compensation offered will be determined by factors such as location, level, job-related knowledge, skills, and experience. Range $75/hr - $85/hr.