Silicon Development & Physical Design Engineer

Team Description: 

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Responsibilities and Description: 

Silicon Development & Physical Design Engineer will be responsible for technical support and operations on silicon development, which includes PDK acquisition and maintenance, foundation IP (standard cell library, I/O library) set-up, CAD tool set-up for physical design & verification, physical design rule development for advanced silicon packaging and ESD protection. This role will be also responsible for the complete process of physical design, which includes the development of parameterized layout cells for custom analog/mixed-signal/RF IPs, the synthesis of register-transfer level (RTL) digital design into silicon, the physical verification of IPs using foundry design rules, process variations, power rail & signal integrity, and ESD robustness towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience will be preferred.

Key Qualifications: (MUST HAVE)

• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering.
• Minimum 5 years of experience in silicon development and operation, including PDK/IP acquisition, and chip tapeout process management. 
• Deep knowledge on industry standards and practices in physical design including physically aware synthesis flow, floor-planning, and place & route.
• Experience in custom analog IP layout and floor-planning
• Expertise in scripting to automate physical design and verification.
• SystemVerilog, C/C++, Python.

Preferred Qualifications: (NICE TO HAVE)

• Experience in coordinating mask tapeout for volume wafer production with foundry.
• Experience in coordinating wafer backend processing with assembly vendors.
• Experience in building chip floor-plan including pin placement, partitions and power grid.
• Experience in hierarchical synthesis, place-and-route and close the design to meet timing, area, and power constraints under UPF.
• Experience in ECO flow to fix timing, noise, and EM IR violations.
• Experience in the physical design verification to debug LVS/DRC/PERC issues at the chip/block level using industry standard tools.
• Experience in board level footprint design support.
• Experience in wafer-level testing with ATE.
• Experience in automating tool flows.
• Understanding of basic SoC architecture.