Silicon Performance Modeling Engineer III (17233-1)

Job Title: Silicon Performance Modeling Engineer III (17233-1)

Type: W2 Contract

Duration: 12 months with scope for extension/conversion

Client: Leading Social Media Company

Location: Redmond, WA

Request ID: 17233-1

**Must have US Work Authorization

What are the top non-negotiable skill sets required for this role?• Experience in writing models using different flavors of TLM, especially, Synopsys' Fast timed (FT) flavor• Experience building TLM 2.0 interfaces to support open core protocol (OCP) and multi-beat protocols like AXI
Duties:• Create bridge modules in System C to translate between different flavors of TLM• Integrate System C components that support different flavors of TLM into Synopsys Platform Architect• Ensure support for multi-beat protocols like AXI when building translation bridges
Skills

Must Have:• 3+ years of experience in C++, System C and transaction level modeling (TLM 2.0)• Experience with performance modeling and analysis for networks on chip (NoCs)• Experience in custom IP block performance/power estimates• Ability to write, manipulate and maintain scripts - Python or similar (Perl, bash/awk, Tcl)
Wish List/ Nice to Have:• MSEE/CS or equivalent experience

Education• Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science• Master's Degree preferred but not required